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Features
* High Performance, Low Power AVR (R) 8-bit Microcontroller * Advanced RISC Architecture
- 131 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 1 MIPS Throughput per MHz - On-chip 2-cycle Multiplier * Data and Non-Volatile Program Memory - 8K Bytes of In-System Programmable Program Memory Flash * Endurance: 10,000 Write/Erase Cycles * Lock bits protection * Optional 2k Bytes Boot Code Section with Independent Lock Bits * In-System Programming by On-chip Boot Program * True Read-While-Write Operation - 512 Bytes of In-System Programmable EEPROM, * 4 bytes page size - 256Bytes Internal SRAM * On Chip Debug support (debugWIRE) * Peripheral Features - One 12-bit High Speed PSC (Power Stage Controllers with extended PSC2 features) * Non overlapping inverted PWM output pins with flexible Dead-Time * Variable PWM duty cycle and frequency * Synchronous update of all PWM registers * Enhanced resolution mode (16 bits) * Additional register for ADC synchronization * Input capture * Four output pins and output matrix - One 12-bit High Speed PSC (Power Stage Controller) * Auto Stop function for event driven PFC implementation * Non overlapping inverted PWM output pins with flexible Dead-Time * Variable PWM duty cycle and frequency * Synchronous update of all PWM registers * Enhanced resolution mode (16 bits) * Input capture - One 16-bit simple General purpose Timer/Counter - 10-bit ADC * up to 11 single ended channels and 1 fully differential ADC channel pair * Programmable gain (5x, 10x, 20x, 40x on differential channel) * Internal reference voltage - One 10-bit DAC - Three Analog Comparator with * Resistor-Array to adjust comparison voltage * DAC to adjust comparison voltage - One SPI - 3 External interrupts - Programmable Watchdog Timer with Separate On-Chip Oscillator
8-bit Microcontroller with 8K Bytes InSystem Programmable Flash AT90PWM81
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* Special Microcontroller Features
- Low Power Idle, Noise Reduction, and Power Down Modes - Power On Reset and Programmable Brown Out Detection - Flag Array in bit-programmable I/O space (3 bytes) - In-System Programmable via SPI Port - Internal low power Calibrated RC Oscillator (8 or 1-MHz, low jitter) - On chip PLL for fast PWM (32, 48, 64-MHz) and CPU (12, 16 MHz); PLL source RC & XTAL - Dynamic clock switch - Temperature sensor * Operating Voltage: 2.7V - 5.5V * Operating Temperature: - -40C to +105C or -40C to +125C * Operating Speed - 5V : 16 MHz core, 64 MHz PLL - 3.3V : 12 MHz core, 48 MHz PLL
1. Products Configuration
The different product configurations are described per Table 1-1. Table 1-1.
Package Pins Flash size EEPROM size RAM size PSC 12 bits with extended features PSC 12 bits Timer 8 bits Timer 16 bits ADC inputs Amplifiers for ADC Temperature sensor Analog Comparators DAC DAC amplifiers UART/DALI SPI
PWM81 configurations
SO20 20 8k 512 256 1 1 1 8 1 1 3 1 1 QFN32 32 8k 512 256 1 1 1 11 1 1 3 1 1
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2. Pin Configurations
Figure 2-1. 20 Pin Packages
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4 Figure 2-2.
AT90PWM81
AT90PWM81 QFN 32 5*5
NC (ACMP3_OUT_A/SS/CLKO) PD0 (PSCOUT20) PB1 (INT0/PSCOUT21) PB2 VCC GND (ACPM1_OUT/PSCIN2/XTAL1) PE1 NC
32-Pin Packages
1 2 3 4 5 6 7 8
NC PE0 (RESET/OCD/INT2) PB0 (PSCOUT23/T1/ACMP3_OUT)
NC (PSCINr/ACMP1M/XTAL2) PE2 (PSCOUTR0/PSCINrB) PD1 (ADC0/ACMP1) PD2 (ADC1/ACMP2_OUT) PD3 (ADC2/ACMP2M/PSCOUTR1) PB3 (ADC3/ACMPM/MOSI) PB4 NC
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
PB7 (ADC9/PSCOUT22/ICP1) PD7 (ADC10/PSCINrA) PB6 (ADC8/MISO/ACMP3) PD6 (AMP0+) NC
24 23 22 21 20 19 18 17
NC PD5 (AMP0-/ADC7) PE3/AREF/ADC6 AGND AVCC PB5 (ADC5/INT1/SCK/ACMP2) PD4 (PSCIN2A/ACMP3M/ADC4) NC
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Table 2-1. : Alternate functions description
NAME, FUNCTION & ALTERNATE FUNCTION Ground: 0V reference Analog Ground: 0V reference for analog part Power Supply: Analog Power Supply: This is the power supply voltage for analog part For a normal use this pin must be connected. Analog Reference : reference for analog converter. This is the reference voltage of the A/D converter. As output, can be used by external analog System Clock Output Reset Input On Chip Debug I/O XTAL Input XTAL Output
MNEMONIC GND AGND VCC AVCC
AREF CLKO RESET# OCD XTAL1 XTAL2
MISO MOSI SCK SS INTn Tn
SPI Master In Slave Out SPI Master Out Slave In SPI Clock SPI Slave Select External interrupt n Timer n clock input
PSCOUTxn PSCINx PSCOUT0n PSCINr
PSCx output n PSCx Digital Input PSC reduced output n PSC reduced Digital Input
ACMPn ACMPMn ACMPM ACOMPn_OUT AMPnAMPn+ ADCn
Analog Comparator n Positive Input Analog Comparator n Negative Input Negative input for analog comparators Analog Comparator n Output Analog Differential Amplifier n Input Channel Analog Differential Amplifier n Input Channel Analog Converter Input Channel n
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Table 2-2.
Pin out description
Port PB0 PE0 PD0 PB1 PB2 VCC GND PE1 PE2
SO 20 QFN32 pins pins GP 1 30 T1 2 31 RESET# OCD, INT2 NA 2 CLKO, SS 3 3 4 4 INT0 5 5 Power Supply 6 6 Ground 7 7 XTAL1 8 10 XTAL2 11 12 13 14 15 18 19 20 21 22 23 26 27 28 29
PSC PSCOUT23
ADC
Analog ACMP3_OUT ACMP3_OUT_A
PSCOUT20 PSCOUT21
PD1 9 PD2 10 PD3 NA PB3 11 PB4 12 PD4 NA PB5 13 AVCC 14 AGND 15 16 PD5 17 PD6 18 PB6 19 PD7 NA PB7 20
PSCIN2 PSCINr PSCOUTR0, PSCINrB ADC0 ADC1 ADC2 ADC3 ADC4 ADC5
ACMP1_OUT ACMP1M
PSCOUTR1 MOSI PSCIN2A INT1, SCK Analog Supply Analog Ground AREF, Analog Ref
ACMP1 ACMP2_OUT ACMP2M ACMPM ACMP3M ACMP2
ADC6 ADC7 ADC8 ADC10 ADC9
MISO ICP1 PSCINrA PSCOUT22
AMP0AMP0+ ACMP3
2.1
2.1.1
Pin Descriptions
VCC Digital supply voltage.
2.1.2
GND Ground.
2.1.3
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the AT90PWM81 as listed on Table 9-3 on page 73.
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2.1.4 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90PWM81 as listed on Table 9-6 on page 76 2.1.5 Port E (P32..0) RESET/ XTAL1/ XTAL2/AREF Port E is an 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 differ from those of the other pins. If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 7-1 on page 50. Shorter pulses are not guaranteed to generate a Reset. Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PE2 can be used as output from the inverting Oscillator amplifier.
The various special features of Port E are elaborated in Table 9-9 on page 78 and Section "Clock Systems and their Distribution", page 27. 2.1.6 AVCC AVCC is the supply voltage pin for the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a lowpass filter.
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3.
3.1
AVR CPU Core
Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
3.2
Architectural Overview
Figure 3-1. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash Program Memory
Program Counter
Status and Control
Instruction Register
32 x 8 General Purpose Registrers
Interrupt Unit SPI Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
ALU
Control Lines
Analog Comparator
I/O Module1
Data SRAM
I/O Module 2
I/O Module n EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM (Store Program Memory) instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher is the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90PWM81 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
3.3
ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description.
3.4
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations.
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Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register - SREG - is defined as:
Bit Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG
* Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set to enabled the interrupts. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the negative flag N and the Two's Complement Overflow Flag V. See the "Instruction Set Description" for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetic. See the "Instruction Set Description" for detailed information. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information.
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3.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * One 8-bit output operand and one 8-bit result input * Two 8-bit output operands and one 8-bit result input * Two 8-bit output operands and one 16-bit result input * One 16-bit output operand and one 16-bit result input Figure 3-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 3-2. AVR CPU General Purpose Working Registers
7 R0 R1 R2 ... R13 General Purpose Working Registers R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 3-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Zpointer registers can be set to index any register in the file. 3.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 3-3. Figure 3-3. The X-, Y-, and Z-registers
15 X-register 7 R27 (0x1B) XH 0 7 R26 (0x1A) XL 0 0
15
YH
YL
0
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Y-register
7 R29 (0x1D)
0
7 R28 (0x1C)
0
15 Z-register 7 R31 (0x1F)
ZH 0 7 R30 (0x1E)
ZL 0
0
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).
3.6
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x100. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
Bit 15 SP15 SP7 7 Read/Write Initial Value R/W R/W 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL
3.7
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 3-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
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Figure 3-4. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
Figure 3-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 3-5. Single Cycle ALU Operation
T1 T2 T3 T4
clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back
3.8
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section "Memory Programming" on page 247 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on page 61. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is PSC2 CAPT - the PSC2 Capture Event. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to "Interrupts" on page 61 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see "Boot Loader Support - Read-WhileWrite Self-Programming" on page 232.
3.8.1
Interrupt Behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed.
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There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG cli sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write
C Code Example
char cSREG; cSREG = SREG; _CLI(); EECR |= (1<When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s)
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C Code Example
_SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */
3.8.2
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.
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4.
Memories
This section describes the different memories in the AT90PWM81. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90PWM81 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
4.1
In-System Reprogrammable Flash Program Memory
The AT90PWM81 contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 4K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The AT90PWM81 Program Counter (PC) is 12 bits wide, thus addressing the 4K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in "Boot Loader Support - Read-While-Write Self-Programming" on page 232. "Memory Programming" on page 247 contains a detailed description on Flash programming in SPI or Parallel programming mode. Constant tables can be allocated within the entire program memory address space (see the LPM - Load Program Memory. Timing diagrams for instruction fetch and execution are presented in "Instruction Execution Timing" on page 12. Figure 4-1. Program Memory Map
Program Memory 0x0000
Application Flash Section
Boot Flash Section 0x0FFF
4.2
SRAM Data Memory
Figure 4-2 shows how the AT90PWM81 SRAM Memory is organized.
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The AT90PWM81 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 512 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 256 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Yor Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 256 bytes of internal data SRAM in the AT90PWM81 are all accessible through all these addressing modes. The Register File is described in "General Purpose Register File" on page 11. Figure 4-2. Data Memory Map
Data Memory
32 Registers 64 I/O Registers 160 Ext I/O Reg. Internal SRAM (256 x 8) 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF 0x0100
0x01FF
4.2.1 SRAM Data Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 4-3.
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Figure 4-3.
On-chip Data SRAM Access Cycles
T1 T2 T3
clkCPU Address Data WR Data RD
Compute Address Address valid
Memory Access Instruction
Next Instruction
4.3
EEPROM Data Memory
The AT90PWM81 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of SPI and Parallel data downloading to the EEPROM, see "Serial Downloading" on page 261, and "Parallel Programming Parameters, Pin Mapping, and Commands" on page 252 respectively.
4.3.1
EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 4-2. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. For details on how to avoid problems in these situations seeSee "Preventing EEPROM Corruption" on page 25. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
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Read
Write
AT90PWM81
4.3.2 The EEPROM Address Registers - EEARH and EEARL
Bit 15 - EEAR7 7 Read/Write Initial Value R R/W 0 X 14 - EEAR6 6 R R/W 0 X 13 - EEAR5 5 R R/W 0 X 12 - EEAR4 4 R R/W 0 X 11 - EEAR3 3 R R/W 0 X 10 - EEAR2 2 R R/W 0 X 9 - EEAR1 1 R R/W 0 X 8 EEAR8 EEAR0 0 R/W R/W X X EEARH EEARL
* Bits 15..9 - Reserved Bits These bits are reserved bits in the AT90PWM81 and will always read as zero. * Bits 8..0 - EEAR8..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 4.3.3 The EEPROM Data Register - EEDR
Bit Read/Write Initial Value 7 EEDR7 R/W 0 6 EEDR6 R/W 0 5 EEDR5 R/W 0 4 EEDR4 R/W 0 3 EEDR3 R/W 0 2 EEDR2 R/W 0 1 EEDR1 R/W 0 0 EEDR0 R/W 0 EEDR
* Bits 7..0 - EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 4.3.4 The EEPROM Control Register - EECR
Bit Read/Write Initial Value 7 NVMBSY R/W X 6 EEPAGE R/W X 5 EEPM1 R/W X 4 EEPM0 R/W X 3 EERIE R/W 0 2 EEMWE R/W 0 1 EEWE R/W X 0 EERE R/W 0 EECR
* Bits 7 - NVMBSY: Non-volatile memory busy The NVMBSY bit is a status bit that indicates that the NVM memory (FLASH, EEPROM, Lock-bits) is busy programming. Once a program operation is started, the bit will be set and it remains set until the program operation is completed. Bits 6 - EEPAGE: EEPROM page access (multiple bytes access mode) Writing EEPAGE to one enables the multiple bytes access mode. That means that several bytes can be programmed simultaneously into the EEPROM. When the EEPAGE bit has been written to one, the EEPAGE bit remains set until an EEPROM program operation is completed. Alternatively the bit is cleared when the temporary EEPROM buffer is flushed in software (see EEPMn bits description). Any write to EEPAGE while EEPE is one will be ignored. See Section "Program multiple bytes in one Atomic operation", page 21 for details on how to load data into the temporary EEPROM page and the usage of the EEPAGE bit.
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* Bits 5..4 - EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEWE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 4-1. While EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 4-1.
EEPM1 0 0 1 1
EEPROM Mode Bits
EEPM0 0 1 0 1 Programming Time 3.4 ms 1.8 ms 1.8 ms - Operation Erase and Write in one operation (Atomic Operation) Erase Only Write Only Flush temporary EEPROM page buffer
* Bit 3 - EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. The interrupt will not be generated during EEPROM write or SPM. * Bit 2 - EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. * Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. 2. 3. 4. 5. 6. Wait until EEWE becomes zero. Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Memory Control and Status Register) becomes zero. Write new EEPROM address to EEAR (optional). Write new EEPROM data to EEDR (optional). Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See "Boot Loader Support - Read-While-Write Self-Programming" on page 232 for details about Boot programming.
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Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. * Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. Table 4-2 lists the typical programming time for EEPROM access from the CPU. Table 4-2.
Symbol EEPROM write (from CPU)
EEPROM Programming Time.
Number of Calibrated RC Oscillator Cycles 26368 Typ Programming Time 3.3 ms
4.3.5
Program multiple bytes in one Atomic operation It is possible to write multiple bytes into the EEPROM. Before initiating a programming (erase/write), the data to be written has to be loaded into the temporary EEPROM page buffer. Writing EEPAGE to one enables a load operation.
When EEPAGE bit is written to one, the temporary EEPROM page buffer is ready for loading. To load data into the temporary EEPROM page buffer, the address and data must be written into EEARL and EEDR respectively. Note that the data is loaded when EEDR is updated. Therefore, the address must be written before data. This operation is repeated until the temporary EEPROM page buffer is filled up or until all data to be written have been loaded. The number of bytes that is loaded must not exceed the temporary EEPROM page size before performing a program operation. Note that it is not possible to write more than one time to each byte in the temporary EEPROM page buffer before executing a program operation. If the same byte is written multiple times, the content in the temporary EEPROM page will be bit wise AND between the written data (i.e. if 0xaa and 0x55 is loaded to the same byte, the result will be 0x00). The temporary EEPROM buffer will be ready for new data after the program operation has completed. Alternatively, the temporary EEPROM buffer is flushed and ready for new data by writing EEPE (within four cycles after EEMPE is written) if the EEPMn bits are 0b11. When the temporary EEPROM buffer is flushed, the EEPAGE bit will be cleared. Loading data into the temporary EEPROM buffer takes three CPU clock cycles. If EEDR is written while EEPAGE is set, the CPU is halted to ensure that the operation takes three cycles.
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The order the different bits and registers should be accessed is: 1 2 3 4 5 Write EEPAGE in EECR (loading of temporary EEPROM buffer is enabled) Write the address bits needed to address bytes within a page into EEARL Write data to EEDR Repeat 2 and 3 above until the buffer is filled up or until all data is loaded Write the remaining address bits into EEARH:EEARL
a. Select which programming mode that should be executed (EEPMn bits). Write the EEPE bit in EECR (within four cycles after EEMPE has been written) to start a program operation. The temporary EEPROM page buffer will auto-erase after program operation is completed. OR b. If an error situation occurred and the loading should be terminated by software: Write EEPM1:0 to 0b11 and trigger the flushing by writing EEPE (within four cycles after EEMPE has been written).
4.4
Fuse Bits
The AT90PWM81 has three Fuse bytes. Table 4-3 - Table 4-5 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, "0", if they are programmed.
Table 4-3.
Extended Low Fuse Byte
Bit No 7 6 5 4 3 2 1 0 Description PSC2 Reset Behavior PSC2 Reset Behavior for OUT22 & 23 PSC Reduced Reset Behavior PSCOUT & PSCOUTR Reset Value PSC & PSCR Inputs Reset Behavior Brown-out Detector trigger level Brown-out Detector trigger level Brown-out Detector trigger level Default Value 1 1 1 1 1 1 (unprogrammed) 0 (programmed) 1 (unprogrammed)
Extended Fuse Byte PSC2RB PSC2RBA PSCRRB PSCRV PSCINRB BODLEVEL2(1) BODLEVEL1(1) BODLEVEL0(1) Notes:
1. See Table 7-2 on page 52 for BODLEVEL Fuse decoding
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Table 4-4.
RSTDISBL(1) DWEN SPIEN(2) WDTON(3) EESAVE BOOTSZ1 BOOTSZ0 BOOTRST Notes:
Fuse High Byte
Bit No 7 6 5 4 3 2 1 0 Description External Reset Disable debugWIRE Enable Enable Serial Program and Data Downloading Watchdog Timer Always On EEPROM memory is preserved through the Chip Erase Select Boot Size (see Table 113 for details) Select Boot Size (see Table 113 for details) Select Reset Vector Default Value 1 (unprogrammed) 1 (unprogrammed) 0 (programmed, SPI programming enabled) 1 (unprogrammed) 1 (unprogrammed), EEPROM not reserved 0 (programmed)(4) 0 (programmed)(4) 1 (unprogrammed)
High Fuse Byte
1. See "Alternate Functions of Port E" on page 78 for description of RSTDISBL Fuse. 2. The SPIEN Fuse is not accessible in serial programming mode. 3. See "Watchdog Timer Configuration" on page 59 for details. 4. The default value of BOOTSZ1..0 results in maximum Boot Size..
Table 4-5.
Low Fuse Byte CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0
(4)
Fuse Low Byte
Bit No 7 6 5 4 3 2 1 0 Description Divide clock by 8 Clock output Select start-up time Select start-up time Select Clock source Select Clock source Select Clock source Select Clock source Default Value 0 (programmed) 1 (unprogrammed) 1 (unprogrammed)(1) 0 (programmed)(1) 0 (programmed)(2) 0 (programmed)(2) 1 (unprogrammed)(2) 0 (programmed)(2)
(3)
Note:
1. The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 5-4 on page 30 for details. 2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 5-1 on page 28 for details. 3. The CKOUT Fuse allows the system clock to be output on PORTD0. See "Clock Output Buffer" on page 34 for details. 4. See "System Clock Prescaler" on page 38 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
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4.4.1
Code examples The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
Assembly Code Example
EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret
C Code Example
void EEPROM_write (unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<24
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example
EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in ret r16,EEDR
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<4.4.2
Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
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4.5
I/O Memory
The I/O space definition of the AT90PWM81 is shown in "Register Summary" on page 298. All AT90PWM81 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bitaccessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM81 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR's, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and peripherals control registers are explained in later sections.
4.6
General Purpose I/O Registers
The AT90PWM81 contains four General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. The General Purpose I/O Registers, within the address range 0x00 - 0x1F, are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
4.6.1
General Purpose I/O Register 0 - GPIOR0
Bit Read/Write Initial Value 7 GPIOR07 R/W 0 6 GPIOR06 R/W 0 5 GPIOR05 R/W 0 4 GPIOR04 R/W 0 3 GPIOR03 R/W 0 2 GPIOR02 R/W 0 1 GPIOR01 R/W 0 0 GPIOR00 R/W 0 GPIOR0
4.6.2
General Purpose I/O Register 1 - GPIOR1
Bit Read/Write Initial Value 7 GPIOR17 R/W 0 6 GPIOR16 R/W 0 5 GPIOR15 R/W 0 4 GPIOR14 R/W 0 3 GPIOR13 R/W 0 2 GPIOR12 R/W 0 1 GPIOR11 R/W 0 0 GPIOR10 R/W 0 GPIOR1
4.6.3
General Purpose I/O Register 2 - GPIOR2
Bit Read/Write Initial Value 7 GPIOR27 R/W 0 6 GPIOR26 R/W 0 5 GPIOR25 R/W 0 4 GPIOR24 R/W 0 3 GPIOR23 R/W 0 2 GPIOR22 R/W 0 1 GPIOR21 R/W 0 0 GPIOR20 R/W 0 GPIOR2
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5. System Clock and Clock Options
The AT90PWM81 provides a large number of clock sources. Those can be divided in two categories: internal and external. After reset, CKSEL Fuses select one clock source. Once the device is running, software clock switching is available on any other clock sources. Some hardware controls are provided for clock switching management but some specific procedures must be observed. Some settings may lead the user to program the device in an inadequate configuration.
5.1
Clock Systems and their Distribution
Figure 5-1 presents the principal clock systems in the AVR and their distribution. All of the clocks may not be active at a given time. In order to reduce power consumption, the clocks from modules not being used can be halted by using different sleep modes or by using features of the dynamic clock switch ("Power Management and Sleep Modes" on page 44 or "Dynamic Clock Switch" on page 35). The clock systems are detailed below. Figure 5-1.
PSC2/PSCR
Clock Distribution
General I/O Modules ADC CPU Core RAM Flash and EEPROM
clk ADC clk I/O clk CPU
AVR Clock Control Unit
clk FLASH CLK PLL Source Clock CLK PLL /4 Prescaler Watchdog Clock
PLL
Reset Logic
Watchdog Timer
PLL Input Multiplexer
Clock switch
CKOUT Fuse
External Clock
(Crystal Oscillator)
Watchdog Oscillator
Calibrated RC Oscillator
CLKO
XTAL1
XTAL2
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5.1.1
CPU Clock - clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. I/O Clock - clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Flash Clock - clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. PLL Clock - clkPLL The PLL clock allows the PSC modules to be clocked directly from a 64/32 MHz clock. A 16 MHz clock is also derived for the CPU. ADC Clock - clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
5.1.2
5.1.3
5.1.4
5.1.5
5.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits (default) or by the CLKSELR register (dynamic clock switch circuit) as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.
Table 5-1.
Device Clocking Options Select(1) , PLL source and PE1 and PE2 functionality
System Clock Ext Clk PLL / 4 RC Osc WD PLL / 4 PLL / 4 RC Osc Ext Osc Ext Osc Ext Osc Ext Osc Ext Osc PLL Input RC Osc RC Osc RC Osc N/A Ext Osc Ext Clk N/A Ext Osc RC Osc RC Osc RC Osc RC Osc
(2)
Device Clocking Option External Clock PLL output divided by 4 : 16 MHz driven by internal RC Calibrated Internal RC Oscillator 8 MHz Internal 128 kHz RC Oscillator (WD) PLL output divided by 4 / PLL driven by External Crystal/Ceramic Resonator PLL output divided by 4/ PLL driven by External clock Calibrated Internal RC Oscillator 1MHz External Crystal/Ceramic Resonator (3.0 - 8.0 MHz) External Crystal/Ceramic Resonator (0.9 - 3.0 MHz) External Crystal/Ceramic Resonator (0.9 - 3.0 MHz) External Crystal/Ceramic Resonator (3.0 - 8.0 MHz) External Crystal/Ceramic Resonator (3.0 - 8.0 MHz)
CKSEL3..0 (3) CSEL3..0 (4) 0000 0001 0010 0011 0100 0101 0110 0111 b 1000 b 1001 b 1010 b 1011 b
PE1 CLKI I/O I/O I/O XTAL1 CLKI I/O XTAL1 XTAL1 XTAL1 XTAL1 XTAL1
PE2 I/O I/O I/O I/O XTAL2 I/O I/O XTAL2 XTAL2 XTAL2 XTAL2 XTAL2
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Table 5-1. Device Clocking Options Select(1) , PLL source and PE1 and PE2 functionality
System Clock Ext Osc Ext Osc Ext Osc Ext Osc PLL Input RC Osc RC Osc RC Osc RC Osc
(2)
Device Clocking Option External Crystal/Ceramic Resonator (3.0 - 8.0 MHz) External Crystal/Ceramic Resonator (3.0 - 8.0 MHz) External Crystal/Ceramic Resonator (8.0 - 16.0 MHz) External Crystal/Ceramic Resonator (8.0 - 16.0 MHz) Note:
CKSEL3..0 (3) CSEL3..0 (4) 1100 b 1101 b 1110 b 1111 b
PE1 XTAL1 XTAL1 XTAL1 XTAL1
PE2 XTAL2 XTAL2 XTAL2 XTAL2
1. For all fuses "1" means unprogrammed while "0" means programmed. 2. PLL must be driven by a nominal 8 MHz clock source 3. Flash Fuse bits. 4. CLKSELR register bits. 5. Ext Osc : External Osc 6. RC Osc : Internal RC Oscillator (1 MHz or 8 MHz) 7. WD : Internal Watch Dog RC Oscillator 128 kHz 8. Ext Clk : External Clock Input
The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down, or when a new clock source is enabled by the dynamic clock switch circuit, the selected clock source is used to time the start-up, ensuring stable oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 5-2. Table 5-2. Number of Watchdog Oscillator Cycles
Typ. Time-out 4 ms 64 ms Number of Cycles 512 8K (8,192)
5.2.1
Default Clock Source The device will always starts up from reset using the clock source defined by CKSEL Fuses the start-up time defined by SUT Fuses. This configuration is latched in CLKSELR register at reset. The device will always starts up at Power-on using the clock source defined by CLKSELR register (CSEL3..0 and CSUT1:0). The device is shipped with CKSEL Fuses = 0010 b, SUT Fuses = 10 b, and CKDIV8 Fuse programmed. The default clock source setting is therefore the Internal RC Oscillator running at 8 MHz with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer. This set-up must be taken into account when using ISP tools.
5.2.2
Calibrated Internal RC Oscillator By default, the Internal RC OScillator provides an approximate 8.0 MHz clock or a 1 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user.
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The switch between 8 MHz and 1 MHz is done by the CKRC81 bit in MCUCR register. See "MCU Control Register - MCUCR" on page 41 for more details.The RC oscillator can be accessed by two CKSEL or CSEL configurations. At reset, the CKRC81 bit is initialised with the value compatible with CKSEL value (1 for CKSEL3..0 = 0110, 0 for all other values). The RC oscillator is active for any CKSEL3..0 or CSEL3..0 configuration where it is used as system clock or PLL source clock. The RC oscillator is diabled in the following CKSEL3..0 or CSEL3..0 cases: * 0011 (128k oscillator) * 0100, 0101 (PLL/4 system clock driven by external clock or oscillator) * 1100,1101 (External oscillator) The device is shipped with the CKDIV8 Fuse programmed. See "System Clock Prescaler" on page 38 for more details. This clock may be selected as the system clock by programming the CKSEL Fuses or CSEL field as shown in Table 5-1. If selected, it will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator.The accuracy of this calibration is shown as Factory calibration in Table 24-1 on page 277.
By changing the OSCCAL register from SW, see "OSCCAL - Oscillator Calibration Register" on page 38, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in Table 24-1 on page 277 When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section "Calibration Byte" on page 252. Table 5-3. Internal Calibrated RC Oscillator Operating Modes(1)(3)
Frequency Range(2) (MHz) 7.6 - 8.4 0.95 - 1.05 Notes:
(4)
CKSEL3..0 0010 0010
1. The device is shipped with this option selected. 2. The frequency ranges are preliminary values. Actual values are TBD. 3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. 4. Switch between 8 MHz and 1 MHz is done by CKRC81 bit in MCUCR register.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 5-4 on page 30. Table 5-4. Start-up times for the internal calibrated RC Oscillator clock selection
Start-up Time from Power-down 6 CK 6 CK 6 CK Reserved Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4.1 ms to ensure programming mode can be entered. 2. The device is shipped with this option selected. Additional Delay from Reset (VCC = 5.0V) 14CK
(1)
Power Conditions BOD enabled Fast rising power Slowly rising power
SUT1..0 00 01 10 11
14CK + 4.1 ms 14CK + 65 ms(2)
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5.2.2.1 RC Oscillator calibration at Factory The RC oscillator is calibrated at 3V, 25C for an 8MHz target frequency with an Accuracy +/- 1%. The corresponding value OSCAL (@Amb.) is stored in the signature row and automatically loaded in the OSCAL register at reset. The RC oscillator is monitored at 105C or 125C (versus Product version) with an accuracy within +/- 5% limits. 128 KHz Internal Oscillator The 128 KHz internal Oscillator is a low power Oscillator providing a clock of 128 KHz. The frequency is nominal at 3V and 25C. This clock may be select as the system clock by programming CKSEL Fuses or CSEL field as shown in Table 5-1 on page 28. When this clock source is selected, start-up times are determined by the SUT Fuses or by CSUT field as shown in Table 5-5. Table 5-5.
SUT1..0(1) CSUT1..0(4) 00 01 10 11 Notes: 1. Flash Fuse bits 2. CLKSELR register bits
5.2.3
Start-up Times for the 128 kHz Internal Oscillator
Start-up Time from Power-down 6 CK 6 CK 6 CK Additional Delay from Reset 14CK 14CK + 4 ms 14CK + 64 ms Reserved Recommended Usage BOD enabled Fast rising power Slowly rising power
5.2.4
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 5-2. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 5-6. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 5-2. Crystal Oscillator Connections
C2 C1 XTAL2 XTAL1 GND
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The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by CKSEL3..1 fuses or by CSEL3..1 field as shown in Table 5-6. Table 5-6. Crystal Oscillator Operating Modes
Frequency Range (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 16.0 Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) - 12 - 22 12 - 22 12 - 22
CKSEL3..1(1) CSEL3..1(2) 100(3) 101 110 111 Notes:
1. Flash Fuse bits. 2. CLKSELR register bits. 3. This option should not be used with crystals, only with ceramic resonators.
The CKSEL0 Fuse together with the SUT1..0 Fuses or CSEL0 together with CSUT1..0 field select the start-up times as shown in Table 5-7. Table 5-7.
CKSEL0(1) CSEL0(2) 0 0 0 0 1 1 1 1 Notes:
Start-up Times for the Crystal Oscillator Clock Selection
SUT1..0(1) CSUT1..0(2) 00 01 10 11 00 01 10 11 Start-up Time from Power-down and Power-save 258 CK(3) 258 CK(3) 1K (1024) CK(4) 1K (1024)CK(4) 1K (1024)CK(4) 16K (16384) CK 16K (16384) CK 16K (16384) CK Additional Delay from Reset (Vcc = 5.0V) 14CK + 4.1 ms 14CK + 65 ms 14CK 14CK + 4.1 ms 14CK + 65 ms 14CK 14CK + 4.1 ms 14CK + 65 ms
Recommended Usage Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power
1. Flash Fuse bits. 2. CLKSELR register bits. 3. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 4. These options are intended for use with ceramic resonators and will ensure frequency stability at startup. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.
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5.2.5 External Clock To drive the device from this external clock source, CLKI should be driven as shown in Figure 5-3. To run the device on an external clock, the CKSEL Fuses or CSEL field must be programmed as shown in Table 5-1 on page 28. Figure 5-3. External Clock Drive Configuration
External Clock Signal
CLKI
(XTAL1)
GND
When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT field as shown in Table 5-8. Table 5-8.
SUT1..0 CSUT1..0(2) 00 01 10 11 Notes: 1. Flash Fuse bits. 2. CLKSELR register bits.
(1)
Start-up Times for the External Clock Selection
Start-up Time from Power-down 6 CK 6 CK 6 CK Additional Delay from Reset 14CK 14CK + 4 ms 14CK + 64 ms Reserved Recommended Usage BOD enabled Fast rising power Slowly rising power
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to "System Clock Prescaler" on page 38 for details.
5.2.6
PLL To generate high frequency and accurate PWM waveforms, the `PSC's need high frequency clock input. This clock is generated by a PLL. To keep all PWM accuracy, the frequency factor of PLL must be configured by software.. The internal PLL in AT90PWM81 generates a clock frequency multiplied from nominally 8 MHz input. The source of the 8 MHz PLL input clock can be selected from three possible sources (See the Figure 5-4 on page 34) : * Internal RC Oscillator * Crystal oscillator * External clock The internal PLL is enabled only when the PLLE bit in the register PLLCSR is set. The bit PLOCK from the register PLLCSR is set when PLL is locked. When selected as clock source by fuse, the PLL multiplication factor is initialized at the value of 6, compatible with a 3V supply.
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The PLL is locked on the source oscillator which must remains close to 8 MHz to assure proper lock of the PLL.
Both internal RC Oscillator and PLL are switched off in Power-down and Standby sleep modes Table 5-9.
CKSEL3..0
Start-up Times when the PLL is selected as system clock
SUT1..0 00 01 Start-up Time from Power-down 1K CK 1K CK 1K CK 16K CK 16K CK 16K CK 16K CK 16K CK 1K CK 1K CK 1K CK Additional Delay from Reset (VCC = 5.0V) 14CK 14CK + 4 ms External Crystal or resonator 10 11 00 01 14CK + 64 ms 14CK 14CK 14CK + 4 ms External Clock 10 11 00 14CK + 4 ms 14CK + 64 ms 14CK 14CK + 4 ms 14CK + 64 ms Internal RC Oscillator Clock Source
0100
0101
0001
01 10
Figure 5-4.
PCK Clocking System
OSCCAL CKSEL3..0 PLLE PLLF3..0
Lock Detector
PLOCK
RC OSCILLATOR
8 MHz
PLL *N
CLK PLL
DIVIDE BY 4 CK SOURCE XT AL1 XT AL2 OSCILLATORS
5.2.7
Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse or COUT bit of CLKSELR register has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. Note that the clock will not be output during reset and the normal operation of I/O pin will be overridden when the fuses are programmed. Any clock source can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.
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5.3
5.3.1
Dynamic Clock Switch
Features AT90PWM81 provides a powerful dynamic clock switch that allows users to turn on and off clocks of the device on the fly. The built-in de-glitching circuitry allows clocks to be enabled or disabled asynchronously. This enables efficient power management schemes to be implemented easily and quickly. In a safety application, the dynamic clock switch circuit may continuously monitor the external clock fails. The AT90PWM81 provides one register for Clock Fuse substitution (CLKSELR) and one register to control the dynamic clock switch circuit (CLKCSR). The watchdog is used to monitor external clock source if needed. The control of the dynamic clock switch circuit must be supervised by software. The low level control is performed by hardware through the CLKCSR register. The features are: * Safe commands, to avoid unintentional commands, a special write procedure must be followed to change the CLKCSR register bits (See "CLKCSR - Clock Control & Status Register" on page 41.): * Exclusive action, the actions are controlled by a decoding (command table). The main commands of the dynamic clock switching are: - `Disable Clock Source', - `Enable Clock Source', - `Request for Clock Availability', - `Clock Source Switching', - `Recover System Clock Source'. * Status, a status on the availability of the enabled clock and the code recovering of clock source used to drive the system clock are provided.
5.3.2
Fuses substitution During reset, bits of the Low Fuse Byte are latched in the CLKSELR register. The content of this register can operate as well as the Low Fuse Byte. CKSEL3..0, SUT1..0 and CKOUT fuses are substituted as shown in Figure 5-5 on page 35 and replaced respectively by CSEL3..0, CSUT1:0 and COUT. Clock Source Selection The available codes of clock source is given are in Table 5-1 on page 28. Figure 5-5. Fuses substitution and Clock Source Selection
Fuse: Register:
5.3.3
Fuse Low Byte
Internal Data Bus
CLKSELR
SEL Decodeur
SEL-0 SEL-1 SEL-2
R/W Reg.
CKSEL[3..0]
CLKSEL[3..0] SUT[1..0] CKOUT
CSEL[3..0] CSUT[1..0] COUT
Default
Reset
SEL-n
Selected Configuration
SCLKRq *
()
SUT[1..0]
CKOUT
SEL Encodeur
EN-0 EN-1 EN-2
Clock Switch Current Configuration
SCLKRq * : Command of Clock Control & Status Register
()
EN-n
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When `Enable/Disable Clock Source', `Request for Clock Availability' or `Clock Source Switching' command is entered, the selected configuration provided by the CLKSELR register is latched for each targeted clock source. `Recover System Clock Source' command enables the code recovering of clock source used to drive the system clock. The CKSEL field of CLKSELR register is then updated with this code. There is no information on the SUT used or status on CKOUT. Because the selected configuration is latched at clock source level, it is possible to enable many clock sources at a given time (ex: the internal RC oscillator for system clock + an oscillator with external crystal). The user's software has the responsibility of this management. `Request for Clock Availability' command returns the working order of the clock source addressed. The status is set in the CLKRDY bit of CLKCSR register 5.3.4 Enable/Disable Clock Source `Enable Clock Source' command selects and enables the clock source provided by the setting of CLKSELR register (CSEL3..0 and CSUT1:0). CSEL field will select the clock source and CSUT field will select the start-up time (as CKSEL and SUT fuse bits do it). To be sure that a clock source has been enabled, it will be better to perform a `Request for Clock Availability' command after the `Enable Clock Source' command. `Disable Clock Source' command disables the clock source provided by the setting of CLKSELR register (only CSEL3..0). If the clock source is the one that is used to drive the system clock, the command is not taken into account. 5.3.5 Clock Availability `Request for Clock Availability' command enables an oscillation-counting of the selected source clock, CSEL3..0. The count is provided by CSUT1..0. The clock is declared ready (CLKRDY = 1) when the count is finished. This flag remains unchanged up to a new count. The CLKRDY flag is reset when the count starts. To perform this checking, the CKSEL and CSUT fields should not change all long the operation is running. Two usages are possible: 1. Clock stability before switching Once the new clock source is selected, the count procedure is running. The user (code) should wait for the setting of the CLKRDY flag in CLKSCR register before to perform a switching. Clock available on request AT any time, the user (code) can ask for the availability of a clock source. The user (code) can request it writing the appropriate command in the CLKSCR register. A full status on clock sources then can be done.
2.
5.3.6
Clock Switching To drive the system clock, the user can switch from the current clock source to the following ones (one of them is the current clock source): 1. 2. 3. 4. 5. Calibrated internal RC oscillator 8.0/1.0 MHz, Internal watchdog oscillator 128 kHz, External clock, External Crystal/Ceramic Resonator PLL output divided by four.
The clock switching is performed in a sequence of commands. First, the user (code) must make sure that the new clock source is running. Then the switching command can be entered. At the end, the user (code) 36
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can stop the previous clock source. It will be better to run this sequence once the interrupts disabled. The user (code) has the responsibility of the clock switching sequence. Here is a "light" C-code that describes such a sequence of commands. C Code Example
void ClockSwiching (unsigned char clk-number, unsigned char sut) { #define #define #define #define CLOCK-RECOVER CLOCK-ENABLE CLOCK-SWITCH CLOCK-DISABLE 0x05 0x02 0x04 0x01
unsigned char previous-clk, temp; // Disable interrupts asm ("cli"); temp = SREG; // "Recover System Clock Source" command CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK-RECOVER; previous-clk = CLKSELR & 0x0F; // "Enable Clock Source" command CLKSELR = ((sut << 4 ) & 0x30) | (clk-number & 0x0F); CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK-ENABLE; // Wait for clock availability while ((CLKCSR & (1 << CLKRDY)) == 0); // "Clock Source Switching" command CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK-SWITCH; // Wait for effective switching while (1){ CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK-RECOVER; if ((CLKSELR & 0x0F) == (clk-number & 0x0F)) break; } // "Disable Clock Source" command CLKSELR = previous-clk; CLKCSR = 1 << CLKCCE; CLKCSR = CLOCK-DISABLE; // Re-enable interrupts SREG = temp; asm ("sei"); }
Warning: In the AT90PWM81, only one among the external clock sources can be enabled at a given time and it is not possible to switch from external clock to external oscillator as both sources share one pin. Also, it is not possible to switch the synchronization source of the PLL when the sytem clock is PLL/4. See Table 5-1 on page 28 to identify these cases. As they are two CSEL adresses to access the Calibrated internal RC oscillator 8.0/1.0 MHz, the change between the two frequencies is not allowed by the clock switching features. The CKRC81 bit in MCUCR register must be used for this purpose.
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5.4
5.4.1
System Clock Prescaler
Features The AT90PWM81 system clock can be divided by setting the Clock Prescaler Register - CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 510 on page 39.
5.4.2
Switching Time When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
5.5
5.5.1
Register Description
OSCCAL - Oscillator Calibration Register
Bit Read/Write 7 CAL7 R/W 6 CAL6 R/W 5 CAL5 R/W 4 CAL4 R/W 3 CAL3 R/W 2 CAL2 R/W 1 CAL1 R/W 0 CAL0 R/W OSCCAL
Initial Value
Device Specific Calibration Value
* Bits 7:0 - CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. The factory-calibrated value is automatically written to this register during chip reset, giving an oscillator frequency of 8.0 MHz at 25C. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to any frequency in the range 7.6 - 8.4 MHz within 1% accuracy. Calibration outside that range is not guaranteed. Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail. The CAL7..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL7..0 by 1 will give a frequency increment of less than 0.5% in the frequency range 7.6 - 8.4 MHz.
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5.5.2 CLKPR - Clock Prescaler Register
Bit Read/Write Initial Value 7 CLKPCE R/W 0 6 - R 0 5 - R 0 4 - R 0 3 CLKPS3 R/W 2 CLKPS2 R/W 1 CLKPS1 R/W 0 CLKPS0 R/W CLKPR
See Bit Description
* Bit 7 - CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. * Bits 6:4 - Res: Reserved Bits These bits are reserved bits in the AT90PWM81 and will always read as zero. * Bits 3:0 - CLKPS3:0: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 5-10. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. 2. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting in order not to disturb the procedure. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to "0000". If CKDIV8 is programmed, CLKPS bits are reset to "0011", giving a division factor of eight at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 5-10.
CLKPS3 0 0 0 0 0 0 0 0
Clock Prescaler Select
CLKPS2 0 0 0 0 1 1 1 1 CLKPS1 0 0 1 1 0 0 1 1 CLKPS0 0 1 0 1 0 1 0 1 Clock Division Factor 1 2 4 8 16 32 64 128
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Table 5-10.
CLKPS3 1 1 1 1 1 1 1 1
Clock Prescaler Select (Continued)
CLKPS2 0 0 0 0 1 1 1 1 CLKPS1 0 0 1 1 0 0 1 1 CLKPS0 0 1 0 1 0 1 0 1 Clock Division Factor 256 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
5.5.3
PLL Control and Status Register - PLLCSR
Bit $29 ($29) Read/Write Initial Value 7 - R 0 6 - R 0 5 PLLF3 R/W 0 4 PLLF2 R/W 1 3 PLLF1 R/W 0 2 PLLF0 R/W 0 1 PLLE R/W 0/1 0 PLOCK R 0 PLLCSR
* Bit 7..3 - Res: Reserved Bits These bits are reserved bits in the AT90PWM81 and always read as zero. * Bit 5..2-- PLLF: PLL Factor The PLLF bits is used to select the multiplication factor of the PLL . Table 5-11.
PLLF3..0 7-F 6 5 4 3 2 0-1 Note: PLLF3 is used for debug purpose (must be wired) 8 7 6 5 4
PLL multiplication factor
N+2 PLL frequency MHz Reserved 64 56 48 40 32 Reserved
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* Bit 1 - PLLE: PLL Enable When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is started as PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1. * Bit 0 - PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable CLKPLL for PSC. The time to lock is specified in Table 5-9 on page 34. 5.5.4 MCU Control Register - MCUCR
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 PUD R/W 0 3 RSTDIS R/W 0/1(1) 2 CKRC81 R/W 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
Notes:
1. V alue is Initialized with the fuse CKSEL2 2. Value is initialized with fuses CKSEL3..0 (1 when CKSEL3..0= 0110, 0 in all other cases)
* Bit 2- CKRC81: Frequency Selection of the calibrated 8/1 MHz RC Oscillator Thanks to CKRC81 in MCUCR Sfr, the typical frequency of the calibrated RC oscillator is changed. - When the CKRC81 bit is written to zero, the RC oscillator frequency is 8 MHz. - When the CKRC81 bit is written to one, the RC oscillator frequency is 1 MHz.
Note: Note: Note: This be only can be changed only when the RC oscillator is enabled. When the RC oscillator is used as the PLL source, CKRC81 must not be written to 1. If the RC oscillator is disabled, this bit is cleared by hardware
5.5.5
CLKCSR - Clock Control & Status Register
Bit Read/Write Initial Value 7 CLKCCE R/W 0 6 - R 0 5 - R 0 4 CLKRDY R 0 3 CLKC3 R/W 0 2 CLKC2 R/W 0 1 CLKC1 R/W 0 0 CLKC0 R/W 0 CLKCSR
* Bit 7 - CLKCCE: Clock Control Change Enable The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The CLKCCE bit is only updated when the other bits in CLKCSR are simultaneously written to zero. CLKCCE is cleared by hardware four cycles after it is written or when the CLKCSR bits are written. Rewriting the CLKCCE bit within this time-out period does neither extend the time-out period, nor clear the CLKCCE bit. * Bits 6:5 - Res: Reserved Bits These bits are reserved bits in the AT90PWM81 and will always read as zero. * Bits 4 - CLKRDY: Clock Ready Flag This flag is the output of the `Clock Availability' logic. This flag is reset once the `Request for Clock Availability' command is entered. It is set when `Clock Availability' logic confirms that the (selected) clock is running and is stable. The delay from the request and the flag setting is not fixed, it depends on the clock start-up time, the clock frequency and, of course, if the clock is alive. The user's has itself to do the difference between `no_clock_signal' and `clock_signal_not_yet_available'.
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* Bits 3:0 - CLKC3:0: Clock Control Bits 3 - 0 These bits define the command to provide to the `Clock Switch' module. The special write procedure must be followed to change the CLKC bits (See "Bit 7 - CLKCCE: Clock Control Change Enable" on page 41.). 1. 2. Write the Clock Control Change Enable (CLKCCE) bit to one and all other bits in CLKCSR to zero. Within 4 cycles, write the desired value to CLKCSR register while clearing CLKCCE bit.
Interrupts should be disabled when setting CLKCSR register in order not to disturb the procedure. Table 5-12. Clock command list.
CLKC3..0 0000 b 0001 b 0010 b 0011 b 0100 b 0101 b 0111 b 1xxx b
Clock Command No command Disable clock source Enable clock source Request for clock availability Clock source switch Recover system clock source code CKOUT command No command
5.5.6
Clock Selection Register - CLKSELR
Bit 7 Read/Write Initial Value R 0 6 COUT R/W CKOUT fuse 5 CSUT1 R/W SUT1..0 fuses 4 CSUT0 R/W 3 CSEL3 R/W 2 CSEL2 R/W 1 CSEL1 R/W 0 CSEL0 R/W CLKSELR
CKSEL3..0 fuses
* Bit 7- Res: Reserved Bit This bit is reserved bit in the AT90PWM81 and will always read as zero. * Bit 6 - COUT: Clock Out The COUT bit is initialized with CKOUT Fuse bit. The COUT bit is only used in case of `CKOUT' command. Refer to Section 5.2.7 "Clock Output Buffer" on page 34 for using. In case of `Recover System Clock Source' command, COUT it is not affected (no recovering of this setting). * Bits 5:4 - CSUT1:0: Clock Start-up Time CSUT bits are initialized with the values of SUT Fuse bits. In case of `Enable/Disable Clock Source' command, CSUT field provides the code of the clock start-up time. Refer to subdivisions of Section 5.2 "Clock Sources" on page 28 for code of clock start-up times. In case of `Recover System Clock Source' command, CSUT field is not affected (no recovering of SUT code).
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* Bits 3:0 - CSEL3:0: Clock Source Select CSEL bits are initialized with the values of CKSEL Fuse bits. In case of `Enable/Disable Clock Source', `Request for Clock Availability' or `Clock Source Switch' command, CSEL field gets back the code of the clock source. Refer to Table 5-1 on page 28 and subdivisions of Section 5.2 "Clock Sources" on page 28 for clock source codes. In case of `Recover System Clock Source' command, CSEL field receives the code of the clock source used to drive the Clock Control Unit as described in Figure 5-1 on page 27.
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6.
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application's requirements.
6.1
Sleep Modes
Figure 5-1 on page 27 presents the different clock systems in the AT90PWM81, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 6-1 shows the different sleep modes, their wake up sources. Table 6-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains clkFLASH Oscillators Main Clock Source Enabled Wake-up Sources SPM/EEPROM Ready
Sleep Mode Idle ADC Noise Reduction Powerdown Standby(1) Notes:
X
X X
X X
X X
X X(2) X(2)
X X
X X
X X
X X X X
X
X
X(2)
1. Only recommended with external crystal or resonator selected as clock source. 2. Only level interrupt.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down or Standby) will be activated by the SLEEP instruction. See Table 6-2 on page 47 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
6.2
Idle Mode
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, Analog Comparator, ADC, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halt clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by clearing the ACnEN bit in the Analog Comparator Control and Sta-
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Other/O
INT3..0
clkADC
clkCPU
clkPLL
WDT
ADC
clkIO
PSC
AT90PWM81
tus Register - ACnCON. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
6.3
ADC Noise Reduction Mode
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, Timer/Counter (if their clock source is external - T0 or T1) and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Timer/Counter interrupt, an SPM/EEPROM ready interrupt, an External Level Interrupt on INT2:0 can wake up the MCU from ADC Noise Reduction mode.
6.4
Power-down Mode
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the External Oscillator is stopped, while the External Interrupts and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a PSC Interrupt, an External Level Interrupt on INT2:0 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to "External Interrupts" on page 82 for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL fuses that define the Reset Time-out period, as described in "Clock Sources" on page 28.
6.5
Standby Mode
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.
6.6
Power Reduction Register
The Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. A full predictable behavior of a peripheral is not guaranteed during and after a cycle of stopping and starting of its clock. So its recommended to stop a peripheral before stopping its clock with PRR register. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped.
6.7
Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be 45
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selected so that as few as possible of the device's functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 6.7.1 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to "CROSS REFERENCE REMOVED" for details on ADC operation. Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is NOT automatically disabled, so it should be disabled if not used However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to "Analog Comparator" on page 194 for details on how to configure the Analog Comparator. 6.7.3 Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to "Brown-out Detection" on page 52 for details on how to configure the Brown-out Detector. Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to "Internal Voltage Reference" on page 54 for details on the startup time. Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to "Watchdog Timer" on page 55 for details on how to configure the Watchdog Timer. Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section "I/O-Ports" on page 66 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power.
6.7.2
6.7.4
6.7.5
6.7.6
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For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to "Digital Input Disable Register 1- DIDR1" and "Digital Input Disable Register 0 - DIDR0" on page 202 and page 221 for details. 6.7.7 On-chip Debug System If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the main clock source is enabled, and hence, always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.
6.8
6.8.1
Register description
Sleep Mode Control Register - SMCR The Sleep Mode Control Register contains control bits for power management.
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 SM2 R/W 0 2 SM1 R/W 0 1 SM0 R/W 0 0 SE R/W 0 SMCR
* Bits 3..1 - SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 6-2. Table 6-2.
SM2 0 0 0 0 1 1 1 1 Note:
Sleep Mode Select
SM1 0 0 1 1 0 0 1 1 SM0 0 1 0 1 0 1 0 1 Sleep Mode Idle ADC Noise Reduction Power-down Reserved Reserved Reserved Standby(1) Reserved
1. Standby mode is only recommended for use with external crystals or resonators.
* Bit 1 - SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer's purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 6.8.2 Power Reduction Register - PRR
Bit Read/Write Initial Value 7 PRPSC2 R/W 0 6 R 0 5 PRPSCR R/W 0 4 PRTIM1 R/W 0 3 R 0 2 PRSPI R/W 0 1 R 0 0 PRADC R/W 0 PRR
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* Bit 7 - PRPSC2: Power Reduction PSC2 Writing a logic one to this bit reduces the consumption of the PSC2 by stopping the clock to this module. When waking up the PSC2 again, the PSC2 should be re initialized to ensure proper operation. * Bit 6 - Reserved * Bit 5 - PRPSCR: Power Reduction PSC reduced Writing a logic one to this bit reduces the consumption of the PSCR by stopping the clock to this module. When waking up the PSCR again, the PSCR should be re initialized to ensure proper operation. * Bit 4 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit reduces the consumption of the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the setting of this bit. * Bit 3 - Reserved * Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface Writing a logic one to this bit reduces the consumption of the Serial Peripheral Interface by stopping the clock to this module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation. * Bit 1 - Reserved * .Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit reduces the consumption of the ADC by stopping the clock to this module. The ADC must be disabled before using this function. The analog comparator cannot use the ADC input MUX when the clock of ADC is stopped.
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7.
7.1
7.1.1
System Control and Reset
System Control overview
Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP - Absolute Jump - instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure 7-1 shows the reset logic. Table 7-1 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in "Clock Sources" on page 28.
7.1.2
Reset Sources The AT90PWM81 has four sources of reset: * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). * External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. The external reset pin can be disabled in 2 ways: - By the RSTDISBL fuse. In this case , the SPI programming is disabled - By software using the RSTDIS bit in MCUCR register. In this case , the SPI programming is still active at power up time. * Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. * Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.
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Figure 7-1.
Reset Logic
DATA BUS
MCU Status Register (MCUSR)
Power-on Reset Circuit
BODLEVEL [2..0] Pull-up Resistor Spike Filter
Brown-out Reset Circuit
RSTDIS
Watchdog Oscillator
Clock Generator
CK
PORF BORF EXTRF WDRF
Delay Counters
TIMEOUT
CKSEL[3:0] SUT[1:0]
Table 7-1.
Symbol
Reset Characteristics(1)
Parameter Power-on Reset Threshold Voltage (rising) Condition Min. Typ. 1.4 1.3 0.2Vcc 400 Max. 2.3 2.3 0.85Vcc Units V V V ns
VPOT
Power-on Reset Threshold Voltage (falling)(2) RESET Pin Threshold Voltage Minimum pulse width on RESET Pin 1. Values are guidelines only..
VRST tRST Notes:
2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)
7.1.3
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 7-1. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level.
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Figure 7-2. MCU Start-up, RESET Tied to VCC
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
Figure 7-3.
MCU Start-up, RESET Extended Externally
VPOT
VCC
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
7.1.4
External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 7-1) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - VRST - on its positive edge, the delay counter starts the MCU after the Time-out period - tTOUT - has expired. Figure 7-4. External Reset During Operation
CC
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7.1.5
Brown-out Detection AT90PWM81 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT VHYST/2. Table 7-2. BODLEVEL Fuse Coding(1)(2)
Min VBOT Typ VBOT Max VBOT Units
BODLEVEL 2..0 Fuses 111 110 101 ( default configuration) 100 011 010 001 000 Notes:
Forbidden, BOD must be enabled 4.5 2.7 3.9 4.3 4.4 4.2 2.8 2.5 2.7 2.9 4.6 V V V V V V V
1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a BrownOut Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 010 for Low Operating Voltageand BODLEVEL = 101for High Operating Voltage. 2. Values are guidelines only.
Table 7-3.
Symbol VHYST tBOD Notes:
Brown-out Characteristics(1)
Parameter Brown-out Detector Hysteresis Min Pulse Width on Brown-out Reset Min. Typ. 70 2 Max. Units mV s
1. Values are guidelines only.
When VCC decreases to a value below the trigger level (VBOT- in Figure 7-5), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 7-5), the delay counter starts the MCU after the Time-out period tTOUT has expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in Table 7-3.
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Figure 7-5. Brown-out Reset During Operation
VCC VBOT+
VBOT-
RESET
TIME-OUT
tTOUT
INTERNAL RESET
7.1.6
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 55 for details on operation of the Watchdog Timer. Figure 7-6. Watchdog Reset During Operation
CC
CK
7.2
7.2.1
System Control registers
MCU Status Register - MCUSR The MCU Status Register provides information on which reset source caused an MCU reset.
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUSR
See Bit Description
* Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
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* Bit 2 - BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.
7.2.2
MCU Control Register - MCUCR
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 PUD R/W 0 3 RSTDIS R/W 0 2 CKRC81 R/W 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
* Bit 3- RSTDIS: Reset Pin Disable Thanks to RSTDIS in MCUCR Sfr, the reset function can be disabled, leaving this pin for functional purpose. - When the RSTDIS bit is written to zero, the reset signal is active. - When the RSTDIS bit is written to one, the reset signal is inactive.
7.3
Internal Voltage Reference
AT90PWM81 features an internal bandgap reference. This bandgap reference is used for Brown-out Detection and can be used as analog input for the analog comparators or the ADC. The internal voltage reference for the DAC and/or the ADC and the comparators is derived from this bandgap voltage. see "On Chip voltage Reference and Temperature sensor overview" on page 189 The Vref voltage is configured thanks to the REFS1 and REFS0 bits in the ADMUX register; see "ADC Multiplexer Register - ADMUX" on page 216
7.3.1
Bandgap and Internal Voltage Reference Enable Signals and Start-up Time The bandgap and the internal voltage reference characteristics is given on Table 7-4. To save power, the reference is not always turned on. The bandgap and the internal reference is on during the following situations: 1. 2. 3. 4. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse). When the internal reference is selected (REFS1 = 1) When the bandgap reference is connected to the Analog Comparator. When the ADC is enabled.
Thus, when the BOD is not enabled, after enabling the ADC, comparator or the internal reference, the user must always allow the reference to start up before the output from the Analog Comparator or ADC or
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DAC is used. To reduce power consumption in Power-down mode, the user can avoid the four conditions above to ensure that the reference is turned off before entering Power-down mode. 7.3.2 Voltage Reference Characteristics
Table 7-4.
Symbol VBG tBG IBG Note:
Internal Voltage Reference Characteristics(1)
Parameter Bandgap reference voltage Bandgap reference start-up time Bandgap reference current consumption Condition Min. Typ. 1.1 40 15 Max. Units V s A
1. Values are guidelines only.
7.4
Watchdog Timer
AT90PWM81 has an Enhanced Watchdog Timer (WDT). The main features are: * Clocked from separate On-chip Oscillator * 3 Operating modes
- Interrupt - System Reset - Interrupt and System Reset * Selectable Time-out period from 1ms to 8s * Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
Figure 7-7.
Watchdog Timer
128 KHz OSCILLATOR
OSC/128 OSC/256 OSC/512 OSC/1K
OSC/2K OSC/4K OSC/8K
WDP3
MCU RESET
WDIF INTERRUPT WDIE
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.
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In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset. The "Watchdog Timer Always On" (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows: 1. 2. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation.
The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
Assembly Code Example(1)
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WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in andi out r16, MCUSR r16, (0xff & (0<; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out lds r16, WDTCSR ori r16, (1<C Code Example(1)
void WDT_off(void) { __disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.
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Assembly Code Example(1)
WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR ori ; -ldi ; -sei ret r16, (1<C Code Example(1)
void WDT_Prescaler_Change(void) { __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period; 7.4.1 Watchdog Timer Control Register - WDTCSR
Bit Read/Write Initial Value 7 WDIF R/W 0 6 WDIE R/W 0 5 WDP3 R/W 0 4 WDCE R/W 0 3 WDE R/W X 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCSR
* Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
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* Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied. Table 7-5.
WDTON(1) 0 0 0 0 1 Note:
Watchdog Timer Configuration
WDE 0 0 1 1 x WDIE 0 1 0 1 x Mode Stopped Interrupt Mode System Reset Mode Interrupt and System Reset Mode System Reset Mode Action on Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset
1. For the WDTON Fuse "1" means unprogrammed while "0" means programmed.
* Bit 4 - WDCE: Watchdog Change Enable This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to one, hardware will clear WDCE after four clock cycles. * Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. * Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 7-6 on page 60.
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.
Table 7-6.
WDP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Watchdog Timer Prescaler Select
WDP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Reserved 1 Number of WDT Oscillator Cycles 2K (2048) cycles 4K (4096) cycles 8K (8192) cycles 16K (16384) cycles 32K (32768) cycles 64K (65536) cycles 128K (131072) cycles 256K (262144) cycles 512K (524288) cycles 1024K (1048576) cycles 1K (1024) cycles 512 cycles 256 cycles 128 cycles Typical Time-out at VCC = 5.0V 16 ms 32 ms 64 ms 0.125 s 0.25 s 0.5 s 1.0 s 2.0 s 4.0 s 8.0 s 8ms 4 ms 2 ms 1 ms
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8. Interrupts
This section describes the specifics of the interrupt handling as performed in AT90PWM81. For a general explanation of the AVR interrupt handling, refer to "Reset and Interrupt Handling" on page 13.
8.1
Interrupt Vectors in AT90PWM81
Table 8-1.
Vector No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Reset and Interrupt Vectors
Program Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 Source RESET PSC2 CAPT PSC2 EC PSC2 EEC PSCr CAPT PSCr EC PSCr EEC ANACOMP 0 ANACOMP 1 ANACOMP 2 INT0 TIMER1 CAPT TIMER1 OVF ADC INT1 SPI, STC INT2 WDT EE READY SPM READY Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and Emulation AVR Reset PSC2 Capture Event PSC2 End Cycle PSC2 End of Enhanced Cycle PSC reduced Capture Event PSC reduced End Cycle PSC reduced End of Enhanced Cycle Analog Comparator 0 Analog Comparator 1 Analog Comparator 2 External Interrupt Request 0 Timer/Counter1 Capture Event Timer/Counter1 Overflow ADC Conversion Complete External Interrupt Request 1 SPI Serial Transfer Complete External Interrupt Request 2 Watchdog Time-Out Interrupt EEPROM Ready Store Program Memory Ready
Notes:
1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see "Boot Loader Support - Read-While-Write Self-Programming" on page 232. 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.
Table 8-2 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and
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regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 8-2.
BOOTRST 1 1 0 0 Note:
Reset and Interrupt Vectors Placement in AT90PWM81(1)
IVSEL 0 1 0 1 Reset Address 0x000 0x000 Boot Reset Address Boot Reset Address Interrupt Vectors Start Address 0x001 Boot Reset Address + 0x001 0x001 Boot Reset Address + 0x001
1. The Boot Reset Address is shown in Table 20-7 on page 246. For the BOOTRST Fuse "1" means unprogrammed while "0" means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM81 is:
Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019 0x01A 0x01B 0x01C 0x01F ; rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp RESET PSC2_CAPT PSC2_EC PSC2_EEC PSCR_CAPT PSCR_EC PSCR_EEC ANA_COMP_0 ANA_COMP_1 ANA_COMP_2 EXT_INT0 TIM1_CAPT TIM1_OVF ADC EXT_INT1 SPI_STC EXT_INT2 WDT EE_RDY SPM_RDY Comments ; Reset Handler ; PSC2 Capture event Handler ; PSC2 End Cycle Handler ; PSC2 End Enhanced Cycle Handler ; PSCr Capture event Handler ; PSC0 End Cycle Handler ; PSCr End Enhanced Cycle Handler ; Analog Comparator 0 Handler ; Analog Comparator 1 Handler ; Analog Comparator 2 Handler ; IRQ0 Handler ; Timer1 Capture Handler ; Timer1 Overflow Handler ; ADC Conversion Complete Handler ; IRQ1 Handler ; SPI Transfer Complete Handler ; IRQ2 Handler ; Watchdog Timer Handler ; EEPROM Ready Handler ; Store Program Memory Ready Handler
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0x020RESET: 0x021 0x022 0x023 0x024 0x025 ... ... ldi out ldi out sei ... r16, high(RAMEND); Main program start SPH,r16 SPL,r16 ; Enable interrupts xxx ... ; Set Stack Pointer to top of RAM r16, low(RAMEND)

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM81 is:
Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 ; .org 0xC01 0xC01 0xC02 ... 0xC1F rjmp rjmp ... rjmp PSC2_CAPT PSC2_EC ... SPM_RDY ; PSC2 Capture event Handler ; PSC2 End Cycle Handler ; ; Store Program Memory Ready Handler RESET: ldi out ldi out sei SPH,r16 r16,low(RAMEND) SPL,r16 ; Enable interrupts xxx Comments r16,high(RAMEND); Main program start ; Set Stack Pointer to top of RAM

When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM81 is:
Address Labels Code .org 0x001 0x001 0x002 ... 0x01F ; .org 0xC00 0xC00 RESET: ldi 0xC01 0xC02 0xC03 0xC04 0xC05 out ldi out sei r16,high(RAMEND); Main program start SPH,r16 r16,low(RAMEND) SPL,r16 ; Enable interrupts xxx ; Set Stack Pointer to top of RAM rjmp rjmp ... rjmp PSC2_CAPT PSC2_EC ... SPM_RDY ; PSC2 Capture event Handler ; PSC2 End Cycle Handler ; ; Store Program Memory Ready Handler Comments

When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM81 is:
Address Labels Code ; Comments
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.org 0xC00 0xC00 0xC01 0xC02 ... 0xC1F ; 0xC20 0xC21 0xC22 0xC23 0xC24 0xC25
rjmp rjmp rjmp ... rjmp
RESET PSC2_CAPT PSC2_EC ... SPM_RDY
; Reset handler ; PSC2 Capture event Handler ; PSC2 End Cycle Handler ; ; Store Program Memory Ready Handler
RESET: ldi out ldi out sei
r16,high(RAMEND); Main program start SPH,r16 r16,low(RAMEND) SPL,r16 ; Enable interrupts xxx ; Set Stack Pointer to top of RAM

8.1.1
Moving Interrupts Between Application and Boot Space The MCU Control Register controls the placement of the Interrupt Vector table. MCU Control Register - MCUCR
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 PUD R/W 0 3 RSTDIS R/W 0 2 CKRC81 R/W 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
8.1.2
* Bit 1 - IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section "Boot Loader Support - Read-While-Write Self-Programming" on page 232 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: a. b. Write the Interrupt Vector Change Enable (IVCE) bit to one. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section "Boot Loader Support - Read-While-Write Self-Programming" on page 232 for details on Boot Lock bits.
* Bit 0 - IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
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Assembly Code Example
Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<C Code Example
void Move_interrupts(void) { /* Enable change of Interrupt Vectors */ MCUCR = (1<65
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9.
9.1
I/O-Ports
Introduction
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 9-1. Refer to "Electrical Characteristics(1)" on page 273 for a complete list of parameters. Figure 9-1. I/O Pin Equivalent Schematic
Rpu
Pxn
Logic Cpin
See Figure "General Digital I/O" for Details
All registers and bit references in this section are written in general form. A lower case "x" represents the numbering letter for the port, and a lower case "n" represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in "Register Description for I/O-Ports". Three I/O memory address locations are allocated for each port, one each for the Data Register - PORTx, Data Direction Register - DDRx, and the Port Input Pins - PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable - PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in "Ports as General Digital I/O". Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in "Alternate Port Functions" on page 71. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.
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9.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 9-2. General Digital I/O(1)
PUD
Q
D
DDxn Q CLR
RESET
WDx RDx
1 Pxn
Q D PORTxn Q CLR
0
WPx RESET WRx SLEEP RRx
SYNCHRONIZER
D Q D Q
RPx
PINxn L Q Q
clk I/O
PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clkI/O : I/O CLOCK
WDx: RDx: WRx: RRx: RPx: WPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports.
9.2.1
Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in "Register Description for I/O-Ports" on page 80, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin The port pins are tri-stated when reset condition becomes active, even if no clocks are running.
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 9.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 9.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 9-1 summarizes the control signals for the pin value. Table 9-1.
DDxn 0 0 0 1 1
Port Pin Configurations
PORTxn 0 1 1 0 1 PUD (in MCUCR) X 0 1 X X I/O Input Input Input Output Output Pull-up No Yes No No No Comment Default configuration after Reset. Tri-state (Hi-Z) Pxn will source current if ext. pulled low. Tri-state (Hi-Z) Output Low (Sink) Output High (Source)
9.2.4
Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 9-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 9-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively.
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Figure 9-3. Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the "SYNC LATCH" signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between 1/2 and 11/2 system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 9-4. The out instruction sets the "SYNC LATCH" signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 9-4. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd 0xFF out PORTx, r16 nop 0xFF in r17, PINx
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back
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again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1)
... ; Define pull-ups and set outputs high ; Define directions for port pins ldi ldi out out nop ; Read port pins in ... r16, PINB r16, (1<; Insert nop for synchronization
C Code Example
unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<9.2.5
Digital Input Enable and Sleep Modes As shown in Figure 9-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in "Alternate Port Functions" on page 71. If a logic high level ("one") is present on an Asynchronous External Interrupt pin configured as "Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin" while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change.
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9.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 9-5 shows how the port pin control signals from the simplified Figure 9-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 9-5. Alternate Port Functions(1)
PUOExn PUOVxn
1 0
PUD
DDOExn DDOVxn
1 0
QD DDxn Q CLR
PVOExn PVOVxn
WDx RESET RDx
1 Pxn 0
Q D
1 0
PORTxn
DIEOExn DIEOVxn
1 0
Q CLR
PTOExn WPx
RESET RRx
WRx
SLEEP SYNCHRONIZER
D
SET
RPx
Q
D
Q
PINxn L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
PUD: PULLUP DISABLE WDx: RDx: RRx: WRx: RPx: WPx: clkI/O: DIxn: AIOxn: WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
Table 9-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 9-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.
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Table 9-2.
Signal Name PUOE
Generic Description of Overriding Signals for Alternate Functions
Full Name Pull-up Override Enable Pull-up Override Value Data Direction Override Enable Data Direction Override Value Port Value Override Enable Port Value Override Value Port Toggle Override Enable Digital Input Enable Override Enable Digital Input Enable Override Value Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits. If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit. If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit. If PTOE is set, the PORTxn Register bit is inverted. If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode). If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode). This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bidirectionally.
PUOV
DDOE
DDOV
PVOE
PVOV PTOE
DIEOE
DIEOV
DI
Digital Input
AIO
Analog Input/Output
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. 9.3.1 MCU Control Register - MCUCR
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 PUD R/W 0 3 RSTDIS RW 0 2 CKRC81 R/W 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
* Bit 4 - PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). Se
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9.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 9-3. Table 9-3.
Port Pin PB7
Port B Pins Alternate Functions
Alternate Functions PSCOUT22 Output ICP1 (Timer/Counter1 Input Capture Pin ) ADC9 (Analog Input Channel 9) MISO (SPI Master In Slave Out) ACMP3 (Analog Comparator 3 Positive Input ) ADC8 (Analog Input Channel 8) ADC5 (Analog Input Channel 5) ACMP2 (Analog Comparator 2 Positive Input) INT1(External Interrupt 1 Input) SCK (SPI Clock) MOSI (SPI Master Out Slave In) ADC3 (Analog Input Channel 3) ACMPM reference for analog comparators PSCOUTR1 Output . ADC2 (Analog Input Channel 2) ACMP2M (Analog Comparator 2 Negative Input) INT0 (External Interrupt 0 Input) PSCOUT21 OutpuT PSCOUT20 output T1counter source. PSCOUT23 Output ACMP3_OUT( Analog Comparator3 Output)
PB6
PB5
PB4
PB3
PB2 PB1 PB0
The alternate pin configuration is as follows: * PSCOUT22/ICP1/ADC9 - Bit 7 PSCOUT22: Output 2 of PSC 2 ICP1 - Input Capture Pin1: This pin can act as an input capture pin for Timer/Counter1. ADC9, Analog to Digital Converter, input channel 9. * MISO/ACMP3/ADC8- Bit 6 MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB0. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 and PUD bits. ACMP3, Analog Comparator 3 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. ADC8, Analog to Digital Converter, input channel 8.
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* ADC5/ACMP2/INT1/SCK - Bit 5 ADC5, Analog to Digital Converter, input channel 5. ACMP2, Analog Comparator 2 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. INT1, External Interrupt source 1. This pin can serve as an external interrupt source to the MCU. SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDD4. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD4. When the pin is forced to be an input, the pull-up can still be controlled by the PORT bit. * MOSI/ADC3/ACMPM- Bit 4 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1 When the SPI is enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 and PUD bits. ADC3, Analog to Digital Converter, input channel 3. ACMPM, Analog Comparators Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. * PSCOUTR1/ADC2/ACMP2M- Bit 3 PSCOUTR1: Output 1 of PSCR. ADC2, Analog to Digital Converter, input channel 2. ACMP2M, Analog Comparator 2 Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. * INT0/PSCOUT21 - Bit 2 INT0, External Interrupt source 0. This pin can serve as an external interrupt source to the MCU. PSCOUT21: Output 1 of PSC 2. * PSCOUT20 - Bit 1 PSCOUT20: Output 0 of PSC 2. * T1/PSCOUT23/ACMP3_OUT - Bit 0 T1, Timer/Counter1 counter source. PSCOUT23: Output 3 of PSC 2. ACMP3_OUT, Analog Comparator3 Output.
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Table 9-4 and Table 9-5 relates the alternate functions of Port B to the overriding signals shown in Figure 9-5 on page 71. Table 9-4.
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO
Overriding Signals for Alternate Functions in PB7..PB4
PB7/PSCOUT22/ ICP1/ADC9 PB6/MISO/ ACMP3/ADC8 PB5/ADC5/ ACMP2/INT1/SCK PB4/MOSI/ADC 3/ACMPM
Table 9-5.
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO
Overriding Signals for Alternate Functions in PB3..PB0
PB3/PSCOUTR1/ ADC2/ACMP2M PB2/PSCOUTR1/ ADC2/ACMP2M PB1/ PSCOUT20 PB0/T1/PSCOUT2 3/ACMP3_OUT
The alternate pin configuration is as follows
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9.3.3
Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 9-6. Table 9-6.
Port Pin PD7 PD6 PD5
Port D Pins Alternate Functions
Alternate Function ADC10 (Analog Input Channel 10) PCSINrA (PSCR first Alternate Digital Input ) AMP0+ (Analog Differential Amplifier 0 Input Channel ) AMP0- (Analog Differential Amplifier 0 Input Channel ) ADC7 (Analog Input Channel 7) ACMP3M (Analog Comparator 3 Negative Input) ADC4 (Analog Input Channel 4) PCSIN2A (PSC 2 Digital Input) ADC1 (Analog Input Channel 1) ACMP2_OUT (Analog Comparator 2 Output) ADC0 (Analog Input Channel 0) ACMP1 (Analog Comparator 1 Positive Input) PSCOUTR0 Output 0 PCSINrB (PSCR Second Alternate Digital Input) ACMP3_OUT_A (Analog Comparator 2 Alternate Output) CLKO ( System Clock) SS ( SPI Slave Select)
PD4
PD3 PD2 PD1
PD0
The alternate pin configuration is as follows:
* ADC10/PSCINrA - Bit 7 ADC10, Analog to Digital Converter, input channel 10. PCSINrA, PSCR First Alternate Digital Input. * APM0+ - Bit 6 AMP0+, Analog Differential Amplifier 0 Positive Input Channel. * AMP0-/ADC7 - Bit 5 AMP0-, Analog Differential Amplifier 0 Negative Input Channel. ADC7, Analog to Digital Converter, input channel 7. * ACMP3M/ADC4/PSCIN2A - Bit 4 ACMP3M, Analog Comparator 3 Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. ADC4, Analog to Digital Converter, input channel 4. PCSIN2A, PSC 2 Alternate Digital Input.
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* ADC1/ACMP2_OUT, Bit 3 ADC1, Analog to Digital Converter, input channel 1. ACMP2_OUT, Analog Comparator 2 Output. * ADC0/ACMP1, Bit 2 ADC0, Analog to Digital Converter, input channel 0. ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. * PSCOUTR0/PSCINrB - Bit 1 PSCOUTR0: Output 0 of PSCR. PCSINrB, PSCR Second Alternate Digital Input. * ACMP3_OUT_A/SS/CLKO - Bit 0 ACMP2_OUT_A, Analog Comparator 2 Alternate Output. SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDDn. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDDn. When the pin is forced to be an input, the pull-up can still be controlled by the PORTDn bit. CLKO, Divided System Clock: The divided system clock can be output on this pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTDn and DDDn settings. It will also be output during reset.
Table 9-7 and Table 9-8 relates the alternate functions of Port D to the overriding signals shown in Figure 9-5 on page 71. Table 9-7.
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO
Overriding Signals for Alternate Functions PD7..PD4
PD7/ ADC10/ PSCINrA PD6/APM0+ PD5/AMP0/ADC7 PD4/ACMP3M/ ADC2/PSCIN2A
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Table 9-8.
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO
Overriding Signals for Alternate Functions in PD3..PD0
PD3/ADC1/ ACMP2_OUT PD2/ADC0/ ACMP1 PD1/PSCOUTR0/ PSCINrB PD0/ACMP2_OUT/ SS/CLKO
9.3.4
Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 9-9. Table 9-9.
Port Pin PE2
Port E Pins Alternate Functions
Alternate Function XTAL2: XTAL Output ACMP1M (Analog Comparator 1 Negative Input) PCSINr (PSCR Digital Input) XTAL1: XTAL Input PCSIN2 (PSC 2 Digital Input) ACMP1_OUT (Analog Comparator 1 Output.) RESET (Reset Input) OCD (On Chip Debug I/O) INT2 (External Interrupt 2 Input)
PE1
PE0
The alternate pin configuration is as follows: * AREF/ADC6, Bit 3 AREF: Analog reference voltage. See Table 17-3 on page 217 for the definition of this pin. ADC6, Analog to Digital Converter, input channel 6. This pin can only be used as a digital output pin. It cannot be read as a digital input. * XTAL2/ACMP1M/PSCINr - Bit 2 XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
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ACMP1M, Analog Comparator 1 Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCSINr, PSCR Digital Input. * XTAL1/PSCIN2/ACMP1_OUT - Bit 1 XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. PCSIN2, PSC 2 Digital Input. ACMP1_OUT, Analog Comparator 1 Output. * RESET/OCD/INT2 - Bit 0 RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources. When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin. If PE0 is used as a reset pin, DDE0, PORTE0 and PINE0 will all read 0. INT2, External Interrupt source 2. This pin can serve as an External Interrupt source to the MCU.
Table 9-10 relates the alternate functions of Port E to the overriding signals shown in Figure 9-5 on page 71.
Table 9-10.
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO
Overriding Signals for Alternate Functions in PE2..PE0
PE2/XTAL2/ACM P1M/PSCINr PE1/XTAL1/PSCI N2/ ACMP1_OUT PE0/RESET/OCD/ INT2
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9.4
9.4.1
Register Description for I/O-Ports
Port B Data Register - PORTB
Bit Read/Write Initial Value 7 PORTB7 R/W 0 6 PORTB6 R/W 0 5 PORTB5 R/W 0 4 PORTB4 R/W 0 3 PORTB3 R/W 0 2 PORTB2 R/W 0 1 PORTB1 R/W 0 0 PORTB0 R/W 0 PORTB
9.4.2
Port B Data Direction Register - DDRB
Bit Read/Write Initial Value 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB
9.4.3
Port B Input Pins Address - PINB
Bit Read/Write Initial Value 7 PINB7 R/W N/A 6 PINB6 R/W N/A 5 PINB5 R/W N/A 4 PINB4 R/W N/A 3 PINB3 R/W N/A 2 PINB2 R/W N/A 1 PINB1 R/W N/A 0 PINB0 R/W N/A PINB
9.4.4
Port D Data Register - PORTD
Bit Read/Write Initial Value 7 PORTD7 R/W 0 6 PORTD6 R/W 0 5 PORTD5 R/W 0 4 PORTD4 R/W 0 3 PORTD3 R/W 0 2 PORTD2 R/W 0 1 PORTD1 R/W 0 0 PORTD0 R/W 0 PORTD
9.4.5
Port D Data Direction Register - DDRD
Bit Read/Write Initial Value 7 DDD7 R/W 0 6 DDD6 R/W 0 5 DDD5 R/W 0 4 DDD4 R/W 0 3 DDD3 R/W 0 2 DDD2 R/W 0 1 DDD1 R/W 0 0 DDD0 R/W 0 DDRD
9.4.6
Port D Input Pins Address - PIND
Bit Read/Write Initial Value 7 PIND7 R/W N/A 6 PIND6 R/W N/A 5 PIND5 R/W N/A 4 PIND4 R/W N/A 3 PIND3 R/W N/A 2 PIND2 R/W N/A 1 PIND1 R/W N/A 0 PIND0 R/W N/A PIND
9.4.7
Port E Data Register - PORTE
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 PORTE2 R/W 0 1 PORTE1 R/W 0 0 PORTE0 R/W 0 PORTE
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9.4.8 Port E Data Direction Register - DDRE
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 DDE2 R/W 0 1 DDE1 R/W 0 0 DDE0 R/W 0 DDRE
9.4.9
Port E Input Pins Address - PINE
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 PINE2 R/W N/A 1 PINE1 R/W N/A 0 PINE0 R/W N/A PINE
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10. External Interrupts
The External Interrupts are triggered by the INT2:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers - EICRA (INT2:0). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT2:0 requires the presence of an I/O clock, described in "Clock Systems and their Distribution" on page 27. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 s (nominal) at 5.0V and 25C. The frequency of the Watchdog Oscillator is voltage dependent as shown in the "Electrical Characteristics(1)" on page 273. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in "System Clock and Clock Options" on page 27. If the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt. 10.0.1 External Interrupt Control Register A - EICRA
Bit Read/Write Initial Value 7 R 0 6 R 0 5 ISC21 R/W 0 4 ISC20 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 EICRA
* Bits 7..0 - ISC21, ISC20 - ISC01, ISC00: External Interrupt 2 - 0 Sense Control Bits The External Interrupts 3 - 0 are activated by the external pins INT2:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 10-1. Edges on INT3..INT0 are registered asynchronously.The value on the INT2:0 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. Table 10-1.
ISCn1 0 0 1 1 Note:
Interrupt Sense Control(1)
ISCn0 0 1 0 1 Description The low level of INTn generates an interrupt request. Any logical change on INTn generates an interrupt request The falling edge between two samples of INTn generates an interrupt request. The rising edge between two samples of INTn generates an interrupt request.
1. n = 3, 2, 1 or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
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10.0.2 External Interrupt Mask Register - EIMSK
Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 INT2 R/W 0 1 INT1 R/W 0 0 IINT0 R/W 0 EIMSK
* Bits 2..0 - INT2 - INT0: External Interrupt Request 3 - 0 Enable When an INT2 - INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Register - EICRA - defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. 10.0.3 External Interrupt Flag Register - EIFR
Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 INTF2 R/W 0 1 INTF1 R/W 0 0 IINTF0 R/W 0 EIFR
* Bits 2..0 - INTF2 - INTF0: External Interrupt Flags 3 - 0 When an edge or logic change on the INT2:0 pin triggers an interrupt request, INTF2:0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT2:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT2:0 are configured as level interrupt.
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11. Reduced 16-bit Timer/Counter1
The 16-bit Timer/Counter unit allows accurate program execution timing (event management). The main features are: * * * * *
Clear Timer on Compare Match (Auto Reload) One Input Capture Unit Input Capture Noise Cancelerr External Event Counter Two independent interrupt Sources (TOV1, ICF1)
11.1
Overview
Most register and bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number, and a lower case "x" replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 11-1. For the actual placement of I/O pins, refer to "Pin out description" on page 6. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "16-bit Timer/Counter Register Description" on page 96. The PRTIM1 bit in "Power Reduction Register" on page 45 must be written to zero to enable Timer/Counter1 module.
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Figure 11-1. 16-bit Timer/Counter Block Diagram(1)
Count Clear Control Logic TOVn (Int.Req.) clk Tn Clock Select Edge Detector TOP BOTTOM (Ckio ) Timer/Counter TCNTn Tn
=
=0
DATA BUS
Fixed TOP Values
( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector Noise Canceler ICPn TCCRnB AC1ICE
ICRn
Note:
1. Refer toTable 2-1 on page 5 for Timer/Counter1 pin placement and description.
11.1.1
Registers The Timer/Counter (TCNT1), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section "Accessing 16-bit Registers" on page 86. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure. The Timer/Counter can be clocked internally, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT1). The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by the ICR1 Register, or by a set of fixed values.
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11.1.2
Definitions The following definitions are used extensively throughout the section:
BOTTOM MAX The counter reaches the BOTTOM when it becomes 0x0000. The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the ICR1 Register. The assignment is dependent of the mode of operation.
TOP
11.2
Accessing 16-bit Registers
The TCNT1, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the ICR1 Registers. Note that when using "C", the compiler handles the 16-bit access.
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Assembly Code Examples(1)
... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ...
C Code Examples(1)
unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example(1)
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TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
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The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example(1)
TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; } Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. 11.2.1 Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case.
11.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B).
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11.3.1
External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 11-2 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 11-2.
Tn
T1/T0 Pin Sampling
D LE Q D Q D Q
Tn_sync (To Clock Select Logic)
clk I/O
Synchronization Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled.
11.4
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 11-3 shows a block diagram of the counter and its surroundings. Figure 11-3. Counter Unit Block Diagram
DATA BUS
(8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Control Logic clk Tn Edge Detector Tn
TCNTn (16-bit Counter) ( Ckio ) TOP BOTTOM
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Signal description (internal signals): Count Clear clkT1 TOP BOTTOM Increment TCNT1 by 1. Clear TCNT1 (set all bits to zero). Timer/Counter clock. Signalize that TCNT1 has reached maximum value. Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bit (WGM13) located in the Timer/Counter Control Registers B ( TCCR1B). The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13 bit. TOV1 can be used for generating a CPU interrupt.
11.5
Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the timestamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 11-4. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small "n" in register and bit names indicates the Timer/Counter number.
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Figure 11-4.
Input Capture Unit Block Diagram
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit) WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
ICNC
ICES
ICPnA
Noise Canceler
Edge Detector
ICFn (Int.Req.)
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter's TOP value. In these cases the Waveform Generation mode (WGM13) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 86. 11.5.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (AC1ICE) bit in the Analog Comparator Extended Control Register (AC1ECON). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change.
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Both the Input Capture pin (ICP1) and the Analog Comparator 1 output (AC1O) inputs are sampled using the same technique as for the T1 pin (SeeFigure 11-2 on page 90). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP1 pin. 11.5.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 11.5.3 Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal's duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used).
11.6
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the Waveform Generation mode (WGM1) For detailed timing information refer to "Timer/Counter Timing Diagrams" on page 94.
11.6.1
Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is only set,
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not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt must be used to extend the resolution for the capture unit. 11.6.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13 = 1, previous mode 12), the ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches the ICR1 . The ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 11-5. The counter value (TCNT1) increases until a compare match occurs with ICR1, and then counter (TCNT1) is cleared. Figure 11-5. CTC Mode, Timing Diagram
ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
An interrupt can be generated at each time the counter value reaches the TOP value by using the ICF1 Flag . If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to ICR1 is lower than the current value of TCNT1, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000.
11.7
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 11-6 shows the count sequence close to TOP in various modes.
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Figure 11-6. Timer/Counter Timing Diagram, no Prescaling
clkI/O clkTn
(clk I/O/1)
TCNTn
TOP - 1
TOP
BOTTOM
BOTTOM + 1
ICFn
Figure 11-7 shows the count sequence close to MAX in various modes.. Figure 11-7. Timer/Counter Timing Diagram, no Prescaling
clkI/O clkTn
(clk I/O/1)
TCNTn
MAX-1
MAX
BOTTOM
BOTTOM + 1
TOVn
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11.8
11.8.1
16-bit Timer/Counter Register Description
Timer/Counter1 Control Register B - TCCR1B
Bit Read/Write Initial Value 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 R 0 4 WGM13 R/W 0 3 R 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B
* Bit 7 - ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. * Bit 6 - ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. * Bit 5 - Reserved * Bit 4 - WGM13: Waveform Generation Mode See the table below for the modes definition Table 11-1.
Mode 0 12
Waveform Generation Mode Bit Description
Timer/Counter Mode of Operation Normal CTC TOP 0xFFFF ICR1 TOV1 Flag Set on MAX MAX
WGM13 0 1
* Bit 3 - Reserved * Bit 2:0 - CS12:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 11-2.
Table 11-2.
CS12 0 0 0 0
Clock Select Bit Description
CS11 0 0 1 1 CS10 0 1 0 1 Description No clock source (Timer/Counter stopped). clkI/O/1 (No prescaling) Reserved Reserved
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Table 11-2.
CS12 1 1 1 1
Clock Select Bit Description
CS11 0 0 1 1 CS10 0 1 0 1 Description Reserved Reserved External clock source on T1 pin. Clock on falling edge. External clock source on T1 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 11.8.2 Timer/Counter1 - TCNT1H and TCNT1L
Bit 7 6 5 4 3 2 1 0 TCNT1H TCNT1L R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
TCNT1[15:8] TCNT1[7:0] Read/Write Initial Value R/W 0
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 86. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. 11.8.3 Input Capture Register 1 - ICR1H and ICR1L
Bit 7 ICR1[15:8] ICR1[7:0] Read/Write Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 ICR1H ICR1L
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 86. 11.8.4 Timer/Counter1 Interrupt Mask Register - TIMSK1
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 ICIE1 R/W 0 4 - R 0 3 - R 0 2 - R/W 0 1 - R/W 0 0 TOIE1 R/W 0 TIMSK1
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* Bit 7, 6 - Res: Reserved Bits These bits are unused bits in the AT90PWM81, and will always read as zero. * Bit 5 - ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see XXXX) is executed when the ICF1 Flag, located in TIFR1, is set. * Bit 4, 3, 2,1 - Res: Reserved Bits These bits are unused bits in the AT90PWM81, and will always read as zero. * Bit 0 - TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (see Table 8-1 on page 61) is executed when the TOV1 Flag, located in TIFR1, is set. 11.8.5 Timer/Counter1 Interrupt Flag Register - TIFR1
Bit Read/Write Initial Value 7 - R 0 6 - R 0 5 ICF1 R/W 0 4 - R 0 3 - R 0 2 - R/W 0 1 - R/W 0 0 TOV1 R/W 0 TIFR1
* Bit 7, 6 - Res: Reserved Bits These bits are unused bits in the AT90PWM81, and will always read as zero. * Bit 5 - ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. * Bit 4, 3, 2,1 - Res: Reserved Bits * Bit 0 - TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WG. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
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12. Power Stage Controller - (PSCn)
The Power Stage Controller is a high performance waveform controller. The AT90PWM81 includes one PSC2 block.
12.1
Features
* * * * * * * * * * *
PWM waveform generation function (2 complementary programmable outputs) Dead time control Standard mode up to 12 bit resolution Frequency and pulse width Resolution Enhancement Mode (12 + 4 bits) Frequency up to 64 Mhz Conditional Waveform on External Events (Zero Crossing, Current Sensing ...) All on chip PSC synchronization ADC synchronization with digital delay register Input Blanking Overload protection function Abnormality protection function, emergency input to force all outputs to high impedance or in inactive state (fuse configurable) * Center aligned and edge aligned modes synchronization * Fast emergency stop by hardware
12.2
Overview
Many register and bit references in this section are written in general form. * A lower case "n" replaces the PSC number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used, i.e., PSOC2 for accessing PSC 2 Synchro and Output Configuration register and so on. * A lower case "x" replaces the PSC part , in this case A or B. However, when using the register or bit defines in a program, the precise form must be used, i.e., PFRC2A for accessing PSC n Fault/Retrigger 2 A Control register and so on. The purpose of a Power Stage Controller (PSC) is to control power modules on a board. It has two outputs on PSCn and four outputs on PSC2. These outputs can be used in various ways: * "Two Outputs" to drive a half bridge (lighting, DC motor ...) * "One Output" to drive single power transistor (DC/DC converter, PFC, DC motor ...) * "Four Outputs" in the case of PSC2 to drive a full bridge (lighting, DC motor ...) Each PSC has two inputs the purpose of which is to provide means to act directly on the generated waveforms: * Current sensing regulation * Zero crossing retriggering * Demagnetization retriggering * Fault input The PSC can be chained and synchronized to provide a configuration to drive three half bridges. Thanks to this feature it is possible to generate a three phase waveforms for applications such as Asynchronous or BLDC motor drive.
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12.3
PSC Description
Figure 12-1. Power Stage Controller 0 or 1 Block Diagram
PSC Counter
=
OCRnRB
Waveform Generator B
PSCOUTn1
=
DATABUS
OCRnSB
PSC Input Module B
PSCn Input B
Part B
=
OCRnRA
PSC Input Module A
PSCn Input A
=
OCRnSA
Waveform Generator A
PSCOUTn0
Part A
PICRn
PCNFEn PCNFn PCTLn PFRCnB PFRCnA
PASDLYn
PSOCn
Note:
n = 0, 1
The principle of the PSC is based on the use of a counter (PSC counter). This counter is able to count up and count down from and to values stored in registers according to the selected running mode. The PSC is seen as two symmetrical entities. One part named part A which generates the output PSCOUTn0 and the second one named part B which generates the PSCOUTn1 output. Each part A or B has its own PSC Input Module to manage selected input.
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12.3.1 PSC2 Distinctive Feature Figure 12-2. PSC2 versus PSC1&PSC0 Block Diagram
PSC Counter PSCOUTn3
=
OCRnRB
Waveform Generator B
POS23
PSCOUTn1
=
DATABUS
OCRnSB
PSC Input Module B
PSCn Input B
Part A
Output Matrix
=
OCRnRA
PSC Input Module A
PSCn Input A
PSCOUTn2
=
OCRnSA
Waveform Generator A
POS22
PSCOUTn0
Part B
PICRn
PCNFEn PCNFn PCTLn PFRCnB PFRCnA
PASDLYn POM2(PSC2 only) PSOCn
Note:
n=2
PSC2 has two supplementary outputs PSCOUT22 and PSCOUT23. Thanks to a first selector PSCOUT22 can duplicate PSCOUT20 or PSCOUT21. Thanks to a second selector PSCOUT23 can duplicate PSCOUT20 or PSCOUT21. The Output Matrix is a kind of 2*2 look up table which gives the possibility to program the output values according to a PSC sequence (See "Output Matrix" on page 129.) 12.3.2 Output Polarity The polarity "active high" or "active low" of the PSC outputs is programmable. All the timing diagrams in the following examples are given in the "active high" polarity.
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12.4
Signal Description
Figure 12-3. PSC External Block View
CLK PLL CLK I/O SYnI n StopOut
OCRnR B[11:0] OCRnSB[11:0] OCRnR A[11:0] OCRnSA[11:0] OCRnR B[15:12] (FlankWidth Modulation) PICRn[11:0] IRQ PSC n
12 12 12 12 4
PSCOUT n0 PSCOUT n1 PSCOUT n2 PSCOUT n3
(1)
(1)
12
2 2
PSCINn Analog Comparator n Output
StopIn SYnO ut
PSCnASY
Note:
1. available only for PSC2 2. n = 0, 1 or 2
12.4.1
Input Description Table 12-1.
Name OCRnRB[11 :0] OCRnSB[11 :0] OCRnRA[1 1:0] OCRnSA[11 :0]
Internal Inputs Description
Compare Value which Reset Signal on Part B (PSCOUTn1) Compare Value which Set Signal on Part B (PSCOUTn1) Compare Value which Reset Signal on Part A (PSCOUTn0) Compare Value which Set Signal on Part A (PSCOUTn0)
Type Width
Register 12 bits Register 12 bits Register 12 bits Register 12 bits
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Name OCRnRB[1 5:12] CLK I/O CLK PLL SYnIn StopIn Note:
Description
Frequency Resolution Enhancement value (Flank Width Modulation) Clock Input from I/O clock Clock Input from PLL Synchronization In (from adjacent PSC) Stop Input (for synchronized mode)
(1)
Type Width
Register 4 bits Signal Signal Signal Signal
1. See Figure 12-41 on page 131
Table 12-2.
Name PSCINn from 1st A C PSCINnA from 2nd A C
Block Inputs Description
Input 0 used for Retrigger or Fault functions Input 1 used for Retrigger or Fault functions Input 2 used for Retrigger or Fault functions Input 3 used for Retrigger or Fault functions
Type Width
Signal Signal Signal Signal
12.4.2
Output Description Table 12-3.
Name PSCOUTn0 PSCOUTn1 PSCOUTn2 (PSC2 only) PSCOUTn3(P SC2 only)
Block Outputs Description
PSC n Output 0 (from part A of PSC) PSC n Output 1 (from part B of PSC) PSC n Output 2 (from part A or part B of PSC) PSC n Output 3 (from part A or part B of PSC)
Type Width
Signal Signal Signal Signal
Table 12-4.
Name SYnOut PICRn [11:0] IRQPSCn PSCnASY StopOut
Internal Outputs Description
Synchronization Output(1) PSC n Input Capture Register Counter value at retriggering event PSC Interrupt Request : three sources, overflow, fault, and input capture ADC Synchronization (+ Amplifier Syncho. )(2) Stop Output (for synchronized mode)
Type Width
Signal Register 12 bits Signal Signal
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Note:
1. See Figure 12-41 on page 131 2. See "Analog Synchronization" on page 130.
12.5
12.5.1
Functional Description
Waveform Cycles The waveform generated by PSC can be described as a sequence of two waveforms. The first waveform is relative to PSCOUTn0 output and part A of PSC. The part of this waveform is subcycle A in the following figure. The second waveform is relative to PSCOUTn1 output and part B of PSC. The part of this waveform is sub-cycle B in the following figure. The complete waveform is ended with the end of sub-cycle B. It means at the end of waveform B. Figure 12-4. Cycle Presentation in 1, 2 & 4 Ramp Mode
PSC Cycle Sub-Cycle A Sub-Cycle B
4 Ramp Mode Ramp A0 Ramp A1 Ramp B0 Ramp B1
2 Ramp Mode
Ramp A
Ramp B
1 Ramp Mode
UPDATE
Figure 12-5.
Cycle Presentation in Centered Mode
PSC Cycle
Centered Mode
UPDATE
Ramps illustrate the output of the PSC counter included in the waveform generators. Centered Mode is like a one ramp mode which count down up and down. Notice that the update of a new set of values is done regardless of ramp Mode at the top of the last ramp.
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12.5.2 Running Mode Description Waveforms and length of output signals are determined by Time Parameters (DT0, OT0, DT1, OT1) and by the running mode. Four modes are possible : - Four Ramp mode - Two Ramp mode - One Ramp mode - Center Aligned mode 12.5.2.1 Four Ramp Mode In Four Ramp mode, each time in a cycle has its own definition Figure 12-6. PSCn0 & PSCn1 Basic Waveforms in Four Ramp mode
OCRnRA OCRnSB
0
PSC Counter OCRnSA
0
OCRnRB
On-Time 0
On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 0 PSC Cycle
Dead-Time 1
The input clock of PSC is given by CLKPSC. PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and Dead-Time 1 values with : On-Time 0 = OCRnRAH/L * 1/Fclkpsc On-Time 1 = OCRnRBH/L * 1/Fclkpsc Dead-Time 0 = (OCRnSAH/L + 2) * 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L + 2) * 1/Fclkpsc
Note: Minimal value for Dead-Time 0 and Dead-Time 1 = 2 * 1/Fclkpsc
12.5.2.2
Two Ramp Mode In Two Ramp mode, the whole cycle is divided in two moments One moment for PSCn0 description with OT0 which gives the time of the whole moment One moment for PSCn1 description with OT1 which gives the time of the whole moment
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Figure 12-7.
PSC Counter
PSCn0 & PSCn1 Basic Waveforms in Two Ramp mode
OCRnRA OCRnSA
0 0
OCRnRB OCRnSB
On-Time 0
On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 0 PSC Cycle
Dead-Time 1
PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and Dead-Time 1 values with : On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH/L + 1) * 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L + 1) * 1/Fclkpsc
Note: Minimal value for Dead-Time 0 and Dead-Time 1 = 1/Fclkpsc
12.5.2.3
One Ramp Mode In One Ramp mode, PSCOUTn0 and PSCOUTn1 outputs can overlap each other.
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Figure 12-8. PSCn0 & PSCn1 Basic Waveforms in One Ramp mode
OCRnRB OCRnSB PSC Counter OCRnSA
0
OCRnRA
On-Time 0
On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 0 PSC Cycle
Dead-Time 1
On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH/L + 1) * 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L - OCRnRAH/L) * 1/Fclkpsc
Note: Minimal value for Dead-Time 0 = 1/Fclkpsc
12.5.2.4
Center Aligned Mode In center aligned mode, the center of PSCn00 and PSCn01 signals are centered.
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Figure 12-9.
PSCn0 & PSCn1 Basic Waveforms in Center Aligned Mode
OCRnRB OCRnSB OCRnSA PSC Counter
0
On-Time 0 On-Time 1 On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time PSC Cycle
Dead-Time
On-Time 0 = 2 * OCRnSAH/L * 1/Fclkpsc On-Time 1 = 2 * (OCRnRBH/L - OCRnSBH/L + 1) * 1/Fclkpsc Dead-Time = (OCRnSBH/L - OCRnSAH/L) * 1/Fclkpsc PSC Cycle = 2 * (OCRnRBH/L + 1) * 1/Fclkpsc
Note: Minimal value for PSC Cycle = 2 * 1/Fclkpsc
OCRnRAH/L is not used to control PSC Output waveform timing. Nevertheless, it can be useful to adjust ADC synchronization (See "Analog Synchronization" on page 130.). Figure 12-10. Run and Stop Mechanism in Centered Mode
OCRnRB OCRnSB OCRnSA PSC Counter
0
Run
PSCOUTn0
PSCOUTn1
Note:
See "PSC 2 Control Register - PCTL2" on page 139.(or PCTL1 or PCTL2)
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12.5.3 Fifty Percent Waveform Configuration When PSCOUTn0 and PSCOUTn1 have the same characteristics, it's possible to configure the PSC in a Fifty Percent mode. When the PSC is in this configuration, it duplicates the OCRnSBH/L and OCRnRBH/L registers in OCRnSAH/L and OCRnRAH/L registers. So it is not necessary to program OCRnSAH/L and OCRnRAH/L registers.
12.6
Update of Values
The update of PSC waveform registers are done in the following way: * Immediately when the PSC is stopped * At the PSC end of cycle when the PSC is running * At the PSC end of cycle following the required condition when LOCK or AUTOLOCK modes are used. To avoid asynchronous and incoherent values in a cycle, if an update of one of several values is necessary, all values can be updated at the same time at the end of the cycle by the PSC. The new set of values is calculated by software and the update is initiated by software. Figure 12-11. Update at the end of complete PSC cycle.
Regulation Loop Calculation Software Writting in PSC Registers Request for an Update
Cycle With Set i PSC
Cycle With Set i
Cycle With Set i
Cycle With Set i Cycle With Set j
End of Cycle
The software can stop the cycle before the end to update the values and restart a new PSC cycle. 12.6.1 Value Update Synchronization New timing values or PSC output configuration can be written during the PSC cycle. Thanks to LOCK and AUTOLOCK configuration bits, the new whole set of values can be taken into account with the following conditions: * When AUTOLOCK configuration is selected, the update of the PSC internal registers will be done at the end of the PSC cycle following a write in the Output Compare Register RB. The AUTOLOCK configuration bit is taken into account at the end of the first PSC cycle. * When LOCK configuration bit is set, there is no update. The update of the PSC internal registers will be done at the end of the PSC cycle if the LOCK bit is released to zero. The registers which update is synchronized thanks to LOCK and AUTOLOCK are PSOCn, POM2, OCRnSAH/L, OCRnRAH/L, OCRnSBH/L and OCRnRBH/L. See these register's description starting on page 134. When set, AUTOLOCK configuration bit prevails over LOCK configuration bit. See "PSC 2 Configuration Register - PCNF2" on page 135.
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12.7
Enhanced Resolution
Lamp Ballast applications need an enhanced resolution down to 50Hz. The method to improve the normal resolution is based on Flank Width Modulation (also called Fractional Divider). Cycles are grouped into frames of 16 cycles. Cycles are modulated by a sequence given by the fractional divider number. The resulting output frequency is the average of the frequencies in the frame. The fractional divider (d) is given by OCRnRB[15:12]. The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0) and PSCOUTn1 On Time + Dead Time (OT1+DT1) values. These values are 12 bits numbers. The frequency adjustment can only be done in steps like the dedicated counters. The step width is defined as the frequency difference between two neighboring PSC frequencies. It is possible to apply the Flank Width Modulation (FWM) on RB, RB+RA, SB, SB+SA. The selection is done bit the bits PBFMn0 and PBFMn. According to the ramp mode and the enhanced resolution mode (defined by PBFMn1:0), the frequency difference f can take three different values:
f = 0
f PSC f PSC 1 f1 = f1 - f2 = ---------- - ----------- = f PSC x ------------------k( k + 1 ) k k+1
f PSC f PSC 2 f2 = f1 - f2 = ---------- - ----------- = f PSC x ------------------k( k + 2 ) k k+2
with k is the number of CLKPSC period in a PSC cycle and is given by the following formula:
f PSC k = ---------f OP
with fOP is the output operating frequency.
Example, in normal mode, with maximum operating frequency 160 kHz and fPLL = 64 Mhz, k equals 400. The resulting resolution is Delta F equals 64MHz / 400 / 401 = 400 Hz.
In enhanced mode, the output frequency is the average of the frame formed by the 16 consecutive cycles. fb1 and fb2 are two neighboring base frequencies.
d16 - d f AVERAGE = -------------- x f b1 + ----- x f b2 16 16
Then the frequency resolution is divided by 16. In the example above, the resolution equals 25 Hz.
16 - d f PLL d- f PLL f AVERAGE = -------------- x --------- + ----- x ----------k 16 k + 1 16
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According to the ramp mode and the enhanced resolution mode (defined by PBFMn1:0), the average frequency deviation f can take three different values:
f ( average ) = 0
d f1 ( average ) = f PSC x ------------------------16k ( k + 1 )
df2 ( average ) = f PSC x ---------------------8k ( k + 2 )
These values are applied according to the running mode and the enhanced resolution mode as per Table 12-5 on page 111; It must be noted that, in one and two ramps modes, it is possible to apply the FWM only on pulse width while keeping a constant frequency.
Table 12-5.
Frequency deviation with Flank Width Modulation PBFMn1:0
00 01 RB+RA f2 f2 f1 f2 10 SB f1 0
(1)
11 SB+SA f2 0 0 f2
Running Mode Four Ramps Two Ramps One Ramp Center aligned 1.
RB f1 f1 f1 f2
0 f2
Note: The modulation is on the pulse width.
12.7.1
Frequency distribution The frequency modulation is done by switching two frequencies in a 16 consecutive cycle frame. These two frequencies are fb1 and fb2 where fb1 is the nearest base frequency above the wanted frequency and fb2 is the nearest base frequency below the wanted frequency. The number of fb1 in the frame is (d-16) and the number of fb2 is d. The fb1 and fb2 frequencies are evenly distributed in the frame according to a predefined pattern. This pattern can be as given in the following table or by any other implementation which give an equivalent evenly distribution. At the end of the 15th cycle (numbered 14 on Table 12-6 ) an interrupt can be generated. This is the case if the bit PEOEPEn (PSC n End Of Enhanced Cycle Interrupt Enable) is set. This allows: * To modify the modulation only on a new enhanced cycle start. * To extend the enhanced modulation accuracy by software.
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Table 12-6.
Distribution of fb2 in the modulated frame
Distribution of fb2 in the modulated frame PWM - cycle Fraction al Divider (d) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
While `X' in the table, fb2 prime to fb1 in cycle corresponding cycle. So for each row, a number of fb2 take place of fb1. Figure 12-12. Resulting Frequency versus d.
fb1
fb2
fOP
d:
12.7.2 12.7.2.1 Modes of Operation Normal Mode The simplest mode of operation is the normal mode. See Figure 12-6. The active time of PSCOUTn0 is given by the OT0 value. The active time of PSCOUTn1 is given by the OT1 value. Both of them are 12 bit values. Thanks to DT0 & DT1 to adjust the dead time between PSCOUTn0 and PSCOUTn1 active signals.
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
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The waveform frequency is defined by the following equation: f CLK_PSCn 1 f PSCn = ----------------------------- = -------------------------------------------------------------------PSCnCycle ( OT0 + OT1 + DT0 + DT1 )
12.7.2.2
Enhanced Mode The Enhanced Mode uses the previously described method to generate a high resolution frequency. Figure 12-13 gives an example of FWM with PBFMn1:0 = 00. Figure 12-13. Enhanced Mode, Timing Diagram
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1+1 DT0
PSCOUTn0 PSCOUTn1 Period
T1 T2
The supplementary step in counting to generate fb2 is added on the PSCn0 signal while needed in the frame according to the fractional divider. SeeTable 12-6, "Distribution of fb2 in the modulated frame," on page 112. The waveform frequency is defined by the following equations: f CLK_PSCn 1 f1 PSCn = ----- = -------------------------------------------------------------------T1 ( OT0 + OT1 + DT0 + DT1 )
f CLK_PSCn 1 f2 PSCn = ----- = -----------------------------------------------------------------------------T2 ( OT0 + OT1 + DT0 + DT1 + 1 )
16 - d df AVERAGE = ----- x f1 PSCn + -------------- x f2 PSCn 16 16
d is the fractional divider factor. The FWM can be applied on different locations within the PSC output waveforms as defined per Table 12-15 on page 137
12.8
PSC Inputs
Part A or B of PSC has its own system to take into account one PSC n internal input. Each part A or B is configured by the PSC n Input A/B Control Register (PFRCnA/B page 140) and the PSC n Extended Configuration Register ((see Section "PSC 2 Configuration Register - PCNF2", page 135) The PSC input module A is shown on Table 12-14
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According to PSC n Input A Control Register (see Section "PSC n Input A Control Register - PFRCnA", page 140), PSC n input A can act as a Retrigger or Fault input. Each part A or B can be triggered by up to four signals as defined per Table 12-18 on page 138 and Table 12-19 on page 139 Part A of PSC has also a blanking module allowing to cancel unwanted transitions which may appear on the PSC n input A during a certain period of time. The blanking start is defined by the bits PASDLKn(2:0) as per Table 12-14 on page 136. The blanking duration is defined by the register PASDLYn. If the blanking is selected by the corresponding PASDLKn(2:0) bit, all transitions which may appears from the blanking start until a time period are ignored. Blanking is level sensitive, i.e. a pulse started in the blanking window and still at active level after the window will generate a valid retriggering event. Figure 12-14. PSC Input Module A
PAO CnA Input Blanking PSC n Input A Digital Filter 1 0 0
PSCINn AC2 Analog O: Comparator Output PSCINnA AC3 Analog O: Comparator Output
0
0 1 1
1 0 1
PFLTEnA
PISELnA1 PISELnA0 OCR SB 3 OSR SA PSC start ycle c PAS DLKn(2:0) 2 1 Blanking S tart PAS DLY
CLK PSC
PCAEnA =0, 4..7 No Blanking PELE / VnA PRFM nA3:0 4
Input Proces sing (retriggering ...)
PSC Cre o (Counter, Wav eform Generator, ...) CLK PSC
Output Control
PSCOUT n0 (PSCOUT n1) (PSCOUT2 (PSCOUT2
PSC input module B is shown on Table 12-15 According to PSC n Input B Control Register (see Section "PSC n Input B Control Register - PFRCnB", page 140), PSC n input B can act as a Retrigger or Fault input.
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Figure 12-15. PSC Input Module B
PAO CnB PSCINn AC2 Analog O: Comparator Output PSCINnA AC3 O:Analog Comparator Output 0 0 0 0 1 1 0 CLK PSC 1 1 PCAEnB PISELnB1 PISELnB0 PELE VnB PRFM nB3:0 4 CLK PSC Input Proces sing (retriggering ...) PFLTEnB PSC n Input B Digital Filter 1
PSC Cre o (Counter, Wav eform Generator, ...) CLK PSC
Output Control
PSCOUT n0 (PSCOUT n1) (PSCOUT2 (PSCOUT2
12.8.1
PSC Retrigger Behavior versus PSC running modes In centered mode, Retrigger Inputs have no effect. In two ramp or four ramp mode, Retrigger Inputs A or B cause the end of the corresponding cycle A or B and the beginning of the following cycle B or A. In one ramp mode, Retrigger Inputs A or B reset the current PSC counting to zero.
12.8.2
Retrigger PSCOUTn0 On External Event PSCOUTn0 output can be reset before end of On-Time 0 on the change on PSCn Input A. PSCn Input A can be configured to do not act or to act on level or edge modes. The polarity of PSCn Input A is configurable thanks to a sense control block. PSCn Input A can be the Output of the analog comparator or the PSCINn input. As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.
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Figure 12-16. PSCOUTn0 retrograde by PSCn Input A (Edge Retriggering)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input A (falling edge)
PSCn Input A (rising edge)
Dead-Time 0
Dead-Time 1
Note:
This example is given in "Input Mode 8" in "2 or 4 ramp mode" See Figure 12-33. for details.
Figure 12-17. PSCOUTn0 retriggered by PSCn Input A (Level Acting)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input A (high level)
PSCn Input A (low level)
Dead-Time 0
Dead-Time 1
Note:
This example is given in "Input Mode 1" in "2 or 4 ramp mode" See Figure 12-22. for details.
12.8.3
Retrigger PSCOUTn1 On External Event PSCOUTn1 output can be reset before end of On-Time 1 on the change on PSCn Input B. The polarity of PSCn Input B is configurable thanks to a sense control block. PSCn Input B can be configured to do not act or to act on level or edge modes. PSCn Input B can be the Output of the analog comparator or the PSCINn input. As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.
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Figure 12-18. PSCOUTn1 retriggered by PSCn Input B (Edge Retriggering)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input B (falling edge)
PSCn Input B (rising edge) Dead-Time 0 Dead-Time 1 Dead-Time 0
Note:
This example is given in "Input Mode 8" in "2 or 4 ramp mode" See Figure 12-33. for details.
Figure 12-19. PSCOUTn1 retriggered by PSCn Input B (Level Acting)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input B (high level)
PSCn Input B (low level) Dead-Time 0 Dead-Time 1 Dead-Time 0
Note:
This example is given in "Input Mode 1" in "2 or 4 ramp mode" See Figure 12-22. for details.
12.8.3.1
Burst Generation
Note:
On level mode, it's possible to use PSC to generate burst by using Input Mode 3 or Mode 4 (See
Figure 12-26. and Figure 12-27. for details.)
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Figure 12-20. Burst Generation
OFF BURST
PSCOUTn0
PSCOUTn1
PSCn Input A (high level)
PSCn Input A (low level)
12.8.4
PSC Input Configuration The PSC Input Configuration is done by programming bits in configuration registers. Filter Enable If the "Filter Enable" bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal. The disable of this function is mainly needed for prescaled PSC clock sources, where the noise cancellation gives too high latency. Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSC clock to deactivate the outputs (emergency protection of external component). Likewise when used as fault input, PSCn Input A or Input B have to go through PSC to act on PSCOUTn0/1/2/3 output. This way needs that CLKPSC is running. So thanks to PSC Asynchronous Output Control bit (PAOCnA/B), PSCnIN0/1 input can deactivate directly the PSC output. Notice that in this case, input is still taken into account as usually by Input Module System as soon as CLKPSC is running. Figure 12-21. PSC Input Flittering
CLKPSC
12.8.4.1
Digital Filter 4 x CLK PSC
PSCn Input A or B
PSC Input Module X
Ouput Stage
PSCOUTnX PIN
12.8.4.2
Signal Polarity One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit description in Section "PSC n Input A Control Register - PFRCnA", page 14012.25.10.
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If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low - In 2- or 4-ramp mode, PSCn Input A is taken into account only during Dead-Time0 and On-Time0 period (respectively Dead-Time1 and On-Time1 for PSCn Input B). - In 1-ramp-mode PSC Input A or PSC Input B act on the whole ramp. 12.8.4.3 Input Mode Operation Thanks to 4 configuration bits (PRFM3:0), it's possible to define the mode of the PSC input. All
Table 12-7.
PSC Input Mode Operation
Description
PRFM3:0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b
PSCn Input has no action on PSC output 12.9See "PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait" on page 120. See "PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait" on page 121. See "PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active" on page 122. See "PSC Input Mode 4: Deactivate outputs without changing timing." on page 123. See "PSC Input Mode 5: Stop signal and Insert Dead-Time" on page 123. See "PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait." on page 124. See "PSC Input Mode 7: Halt PSC and Wait for Software Action" on page 124. See "PSC Input Mode 8: Edge Retrigger PSC" on page 125. See "PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC" on page 126. Reserved : Do not use
See "PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate Output" on page 127. Reserved : Do not use
Notice: All following examples are given with rising edge or high level active inputs.
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12.9
PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait
Figure 12-22. PSCn behavior versus PSCn Input A in Fault Mode 1
DT0 OT0 DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSCOUTn0 PSCOUTn1
PSC Input A PSC Input B
PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSC Input A event occurs, PSC releases PSCOUTn0, waits for PSC Input A inactive state and then jumps and executes DT1 plus OT1.
Figure 12-23. PSCn behavior versus PSCn Input B in Fault Mode 1
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0. When PSC Input B event occurs, PSC releases PSCOUTn1, waits for PSC Input B inactive state and then jumps and executes DT0 plus OT0.
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12.10 PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait
Figure 12-24. PSCn behavior versus PSCn Input A in Fault Mode 2
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0 OT0 DT1 OT1
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSC Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSCn Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus OT1 and then waits for PSC Input A inactive state. Even if PSC Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always completely executed. Figure 12-25. PSCn behavior versus PSCn Input B in Fault Mode 2
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0. When PSC Input B event occurs, PSC releases PSCOUTn1, jumps and executes DT0 plus OT0 and then waits for PSC Input B inactive state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always completely executed.
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12.11 PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active
Figure 12-26. PSCn behavior versus PSCn Input A in Mode 3
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0 OT0 DT1 OT1
DT1 OT1
DT1 OT1
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSC Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus OT1 plus DT0 while PSC Input A is in active state. Even if PSC Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always completely executed. Figure 12-27. PSCn behavior versus PSCn Input B in Mode 3
DT0 PSCOUTn0 PSCOUTn1 OT0 DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT0
OT0
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSC Input B is taken into account during DT1 and OT1 only. It has no effect during DT0 and OT0. When PSC Input B event occurs, PSC releases PSCnOUT1, jumps and executes DT0 plus OT0 plus DT1 while PSC Input B is in active state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always completely executed.
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12.12 PSC Input Mode 4: Deactivate outputs without changing timing.
Figure 12-28. PSC behavior versus PSCn Input A or Input B in Mode 4
DT0 PSCOUTn0 PSCOUTn1 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCn Input A or PSCn Input B
Figure 12-29. PSC behavior versus PSCn Input A or Input B in Fault Mode 4
DT0 PSCOUTn0 PSCOUTn1 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCn Input A or PSCn Input B
PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
12.13 PSC Input Mode 5: Stop signal and Insert Dead-Time
Figure 12-30. PSC behavior versus PSCn Input A in Fault Mode 5
DT1 DT0 DT1 DT0
DT0 PSCOUTn0 PSCOUTn1 OT0 DT0 OT0
DT0
DT1 OT1
PSCn Input A or PSCn Input B
DT1
DT1
OT1
DT0
OT0
DT1
OT1
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Used in Fault mode 5, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
12.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait.
Figure 12-31. PSC behavior versus PSCn Input A in Fault Mode 6
DT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B OT0 DT0 OT0 DT0 OT0
DT1 OT1
DT1
OT1
DT1
OT1
Used in Fault mode 6, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
12.15 PSC Input Mode 7: Halt PSC and Wait for Software Action
Figure 12-32. PSC behavior versus PSCn Input A in Fault Mode 7
DT0 PSCOUTn0 PSCOUTn1 OT0 DT0 OT0 DT0 OT0
DT1
OT1
DT1
OT1
PSCn Input A or PSCn Input B Software Action (1)
Note:
1. Software action is the setting of the PRUNn bit in PCTLn register.
Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
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12.16 PSC Input Mode 8: Edge Retrigger PSC
Figure 12-33. PSC behavior versus PSCn Input A in Mode 8
DT0 PSCOUTn0 PSCOUTn1 OT0 DT0 OT0 DT0 OT0
DT1
OT1
DT1
OT1
DT1
OT1
PSCn Input A
The output frequency is modulated by the occurrence of significative edge of retriggering input.
Figure 12-34. PSC behavior versus PSCn Input B in Mode 8
DT0 PSCOUTn0 PSCOUTn1 OT0 DT0 OT0 DT0 OT0
DT1
OT1
DT1
OT1
DT1
OT1
PSCn Input B or PSCn Input B
The output frequency is modulated by the occurrence of significative edge of retriggering input. The retrigger event is taken into account only if it occurs during the corresponding On-Time. Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSC doesn't jump to the opposite dead-time.
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12.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC
Figure 12-35. PSC behavior versus PSCn Input A in Mode 9
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSCn Input A
The output frequency is not modified by the occurrence of significative edge of retriggering input. Only the output is deactivated when significative edge on retriggering input occurs. Note: In this mode the output of the PSC becomes active during the next ramp even if the Retrigger/Fault input is active. Only the significative edge of Retrigger/Fault input is taken into account.
Figure 12-36. PSC behavior versus PSCn Input B in Mode 9
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSCn Input B
The retrigger event is taken into account only if it occurs during the corresponding On-Time.
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12.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate Output
Figure 12-37. PSC behavior versus PSCn Input A in Mode 14
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSCn Input A
The output frequency is not modified by the occurrence of significative edge of retriggering input.
Figure 12-38. PSC behavior versus PSCn Input B in Mode 14
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSCn Input B
The output is deactivated while retriggering input is active. The output of the PSC is set to an inactive state and the corresponding ramp is not aborted. The output stays in an inactive state while the Retrigger/Fault input is active. The PSC runs at constant frequency.
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12.18.1
Available Input Mode according to Running Mode Some Input Modes are not consistent with some Running Modes. So the table below gives the input modes which are valid according to running modes. Table 12-8. Available Input Modes according to Running Modes
1 Ramp Mode Valid Do not use Do not use Valid Do not use Do not use Valid Valid Valid 2 Ramp Mode Valid Valid Valid Valid Valid Valid Valid Valid Valid 4 Ramp Mode Valid Valid Valid Valid Valid Valid Valid Valid Valid Centered Mode Do not use Do not use Do not use Valid Do not use Do not use Valid Do not use Do not use
Input Mode Number : 1 2 3 4 5 6 7 8 9 10 11
Do not use 12 13 14 15 Valid Do not use Valid Valid Do not use
12.18.2
Event Capture The PSC can capture the value of time (PSC counter) when a retrigger event or fault event occurs on PSC inputs. This value can be read by software in PICRnH/L register.
12.18.3
Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the PICR1 Register before the next event occurs, the PICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the PICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
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12.19 PSC2 Outputs
12.19.1 Output Matrix PSC2 has an output matrix which allow in 4 ramp mode to program a value of PSCOUT20 and PSCOUT21 binary value for each ramp. Table 12-9. Output Matrix versus ramp number
Ramp 0 PSCOUT20 PSCOUT21 POMV2A0 POMV2B0 Ramp 1 POMV2A1 POMV2B1 Ramp 2 POMV2A2 POMV2B2 Ramp 3 POMV2A3 POMV2B3
PSCOUT2m takes the value given in Table 12-9. during all corresponding ramp. Thanks to the Output Matrix it is possible to generate all kind of PSCOUT20/PSCOUT21 combination. When Output Matrix is used, the PSC n Output Polarity POPn has no action on the outputs. 12.19.2 PSCOUT22 & PSCOUT23 Selectors PSC 2 has two supplementary outputs PSCOUT22 and PSCOUT23. According to POS22 and POS23 bits in PSOC2 register, PSCOUT22 and PSCOUT23 duplicate PSCOUT20 and PSCOU21. If POS22 bit in PSOC2 register is clear, PSCOUT22 duplicates PSCOUT20. If POS22 bit in PSOC2 register is set, PSCOUT22 duplicates PSCOUT21. If POS23 bit in PSOC2 register is clear, PSCOUT23 duplicates PSCOUT21. If POS23 bit in PSOC2 register is set, PSCOUT23 duplicates PSCOUT20. Figure 12-39. PSCOUT22 and PSCOUT23 Outputs
Waveform Generator A 0 1 Output Matrix 1 POS22 POS23
PSCOUT20
PSCOUT22
PSCOUT23 0 Waveform Generator B PSCOUT21
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12.20 Analog Synchronization
PSC generates a signal to synchronize the sample and hold or the ADC start; synchronization is mandatory for measurements. This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs as defined per Table 12-11 on page 133 and Table 12-12 on page 134. The signal can be shifted by a digital delay defined by the register PASDLY. The shifting clock can be either Clkpsc or Clkpsc/4, as described per Bit 7, 6, 5- PASDLKn(2:0): Analog Synchronization Output Delay or Input Blanking select .
Figure 12-40. Analog synchronization
OCRnRA match A Trig/Fault OCRnSA match OCRnRB match B Trig/Fault
OCRnSB match
00
01
10
11
PSYNCn(1:0)
CLKPSCn/8 CLKPSCn/4 CLKPSCn/2 CLKPSCn
7 6 5 4
Digital Delay PASDLYn
0
PSCnASY
1
PASDLKn(2:0) PASDLKn(2)
12.21 Interrupt Handling
As each PSC can be dedicated for one function, each PSC has its own interrupt system (vector ...) List of interrupt sources: * Counter reload (end of On Time 1) * End of Enhanced Cycle * PSC Input event (active edge or at the beginning of level configured event) * PSC Mutual Synchronization Error
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12.22 PSC Synchronization
Note : In AT90PWM81, this feature is not relevant and PRUN2, PARUN2 are stuck at zero. 2 or 3 PSC can be synchronized together. In this case, two waveform alignments are possible: * The waveforms are center aligned in the Center Aligned mode if master and slaves are all with the same PSC period (which is the natural use). * The waveforms are edge aligned in the 1, 2 or 4 ramp mode
Figure 12-41. PSC Run Synchronization
SY0In PRUN0 Run PSC0
PARUN0 SY0Out
PSC0
SY1In PRUN1 Run PSC1
PARUN1 SY1Out
PSC1
SY2In PRUN2 Run PSC2
PARUN2 SY2Out
PSC2
If the PSCm has its PARUNn bit set, then it can start at the same time than PSCn-1. PRUNn and PARUNn bits are located in PCTLn register. See "PSC 2 Control Register - PCTL2" on page 139. Note : Do not set the PARUNn bits on the three PSC at the same time. Thanks to this feature, we can for example configure two PSC in slave mode (PARUNn = 1 / PRUNn = 0) and one PSC in master mode (PARUNm = 0 / PRUNm = 0). This PSC master can start all PSC at the same moment ( PRUNm = 1). 12.22.1 Fault events in Autorun mode To complete this master/slave mechanism, fault event (input mode 7) is propagated from PSCn-1 to PSCn and from PSCn to PSCn-1. A PSC which propagate a Run signal to the following PSC stops this PSC when the Run signal is deactivate.
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According to the architecture of the PSC synchronization which build a "daisy-chain on the PSC run signal" between the three PSC, only the fault event (mode 7) which is able to "stop" the PSC through the PRUN bits is transmitted along this daisy-chain. A PSC which receive its Run signal from the previous PSC transmits its fault signal (if enabled) to this previous PSC. So a slave PSC propagates its fault events when they are configured and enabled.
12.23 PSC Clock Sources
PSC must be able to generate high frequency with enhanced resolution. Each PSC has two clock inputs: * CLK PLL from the PLL * CLK I/O Figure 12-42. Clock selection
CLK
PLL 1 CK PRESCALER
CLK
CK/4
CK
CK/32
00
01
10
PCLKSELn
11
CK/256
I/O
0
PPREn1/0
CLK
PSCn
PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source. PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the clock.
Table 12-10.
PCLKSELn 0 0 0 0 1 1 1 1
Output Clock versus Selection and Prescaler
PPREn1 0 0 1 1 0 0 1 1 PPREn0 0 1 0 1 0 1 0 1 CLKPSCn output CLK I/O CLK I/O / 4 CLK I/O / 32 CLK I/O / 256 CLK PLL CLK PLL / 4 CLK PLL / 32 CLK PLL / 256
12.24 Interrupts
This section describes the specifics of the interrupt handling as performed in AT90PWM81.
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12.24.1 List of Interrupt Vector Each PSC provides 3 interrupt vectors * PSCn EC (End of Cycle): When enabled and when a match with OCRnRB occurs * PSCn EEC (End of Enhanced Cycle): When enabled and when a match with OCRnRB occurs at the 15th enhanced cycle * PSCn CAPT (Capture Event): When enabled and one of the two following events occurs : retrigger, capture of the PSC counter or Synchro Error. See "PSC2 Interrupt Mask Register - PIM2" on page 143. .
12.25 PSC Register Definition
Registers are explained for PSC0. They are identical for PSC1. For PSC2 only different registers are described. 12.25.1 PSC 2 Synchro and Output Configuration - PSOC2
Bit Read/Write Initial Value 7 POS23 R/W 0 6 POS22 R/W 0 5 PSYNC21 R/W 0 4 PSYNC20 R/W 0 3 POEN2D R/W 0 2 POEN2B R/W 0 1 POEN2C R/W 0 0 POEN2A R/W 0 PSOC2
* Bit 7 - POS23 : PSCOUT23 Selection (PSC2 only) When this bit is clear, PSCOUT23 outputs the waveform generated by Waveform Generator B. When this bit is set, PSCOUT23 outputs the waveform generated by Waveform Generator A. * Bit 6 - POS22 : PSCOUT22 Selection (PSC2 only) When this bit is clear, PSCOUT22 outputs the waveform generated by Waveform Generator A. When this bit is set, PSCOUT22 outputs the waveform generated by Waveform Generator B. * Bit 5:4 - PSYNCn1:0: Synchronization Out for ADC Selection Select the polarity and signal source for generating a signal which will be sent to the ADC for synchronization. Table 12-11.
PSYNCn1 0 0 1 1
Synchronization Source Description in One/Two/Four Ramp Modes
PSYNCn0 0 1 0 1 Description Send signal on leading edge of PSCOUTn0 (match with OCRnSA) Send signal on trailing edge of PSCOUTn0 (match with OCRnRA or fault/retrigger on part A) Send signal on leading edge of PSCOUTn1 (match with OCRnSB) Send signal on trailing edge of PSCOUTn1 (match with OCRnRB or fault/retrigger on part B)
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Table 12-12.
PSYNCn1 0 0 1 1
Synchronization Source Description in Centered Mode
PSYNCn0 0 1 0 1 Description Send signal on match with OCRnRA (during counting down of PSC). The min value of OCRnRA must be 1. Send signal on match with OCRnRA (during counting up of PSC). The min value of OCRnRA must be 1. no synchronization signal no synchronization signal
* Bit 3 - POEN2D : PSCOUT23 Output Enable (PSC2 only) When this bit is clear, second I/O pin affected to PSCOUT23 acts as a standard port. When this bit is set, second I/O pin affected to PSCOUT23 is connected to the PSC waveform generator B output and is set and clear according to the PSC operation. * Bit 2 - POENnB: PSC n OUT Part B Output Enable When this bit is clear, I/O pin affected to PSCOUTn1 acts as a standard port. When this bit is set, I/O pin affected to PSCOUTn1 is connected to the PSC waveform generator B output and is set and clear according to the PSC operation. * Bit 1 - POEN2C : PSCOUT22 Output Enable (PSC2 only) When this bit is clear, second I/O pin affected to PSCOUT22 acts as a standard port. When this bit is set, second I/O pin affected to PSCOUT22 is connected to the PSC waveform generator A output and is set and clear according to the PSC operation. * Bit 0 - POENnA: PSC n OUT Part A Output Enable When this bit is clear, I/O pin affected to PSCOUTn0 acts as a standard port. When this bit is set, I/O pin affected to PSCOUTn0 is connected to the PSC waveform generator A output and is set and clear according to the PSC operation. 12.25.2 Output Compare SA Register - OCRnSAH and OCRnSAL
Bit 7 - Read/Write Initial Value W 0 6 - W 0 5 - W 0 4 - W 0 3 2 1 0 OCRnSAH OCRnSAL W 0 W 0 W 0 W 0
OCRnSA[11:8]
OCRnSA[7:0]
12.25.3
Output Compare RA Register - OCRnRAH and OCRnRAL
Bit 7 - Read/Write Initial Value W 0 6 - W 0 5 - W 0 4 - W 0 3 2 1 0 OCRnRAH OCRnRAL W 0 W 0 W 0 W 0
OCRnRA[11:8]
OCRnRA[7:0]
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12.25.4 Output Compare SB Register - OCRnSBH and OCRnSBL
Bit 7 - Read/Write Initial Value W 0 6 - W 0 5 - W 0 4 - W 0 3 2 1 0 OCRnSBH OCRnSBL W 0 W 0 W 0 W 0
OCRnSB[11:8]
OCRnSB[7:0]
12.25.5
Output Compare RB Register - OCRnRBH and OCRnRBL
Bit 7 6 5 4 3 2 1 0 OCRnRBH OCRnRBL W 0 W 0 W 0 W 0 W 0 W 0
OCRnRB[15:12] OCRnRB[7:0] Read/Write Initial Value W 0 W 0
OCRnRB[11:8]
Note : n = 0 to 2 according to PSC number. The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the PSC counter value. A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the associated pin. The Output Compare Registers RB contains also a 4-bit value that is used for the flank width modulation. The Output Compare Registers are 16bit and 12-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers.
12.25.6
PSC 2 Configuration Register - PCNF2
Bit Read/Write Initial Value 7 PFIFTY2 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 PCNF2 R/W 0 PCLKSEL2 POME2
PALOCK2 PLOCK2
PMODE21 PMODE20 POP2
The PSC n Configuration Register is used to configure the running mode of the PSC. * Bit 7 - PFIFTYn: PSC n Fifty Writing this bit to one, set the PSC in a fifty percent mode where only OCRnRBH/L and OCRnSBH/L are used. They are duplicated in OCRnRAH/L and OCRnSAH/L during the update of OCRnRBH/L. This feature is useful to perform fifty percent waveforms. * Bit 6 - PALOCKn: PSC n Autolock When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The update of the PSC internal registers will be done at the end of the PSC cycle if the Output Compare Register RB has been the last written. When set, this bit prevails over LOCK (bit 5) * Bit 5 - PLOCKn: PSC n Lock When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2 and the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The update of the PSC internal registers will be done if the LOCK bit is released to zero. 135
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* Bit 4:3 - PMODEn1: 0: PSC n Mode Select the mode of PSC. Table 12-13.
PMODEn1 0 0 1 1
PSC n Mode Selection
PMODEn0 0 1 0 1 Description One Ramp Mode Two Ramp Mode Four Ramp Mode Center Aligned Mode
* Bit 2 - POPn: PSC n Output Polarity If this bit is cleared, the PSC outputs are active Low. If this bit is set, the PSC outputs are active High. * Bit 1 - PCLKSELn: PSC n Input Clock Select This bit is used to select between CLKPF or CLKPS clocks. Set this bit to select the fast clock input (CLKPF). Clear this bit to select the slow clock input (CLKPS). * Bit 0 - POME2: PSC 2 Output Matrix Enable (PSC2 only) Set this bit to enable the Output Matrix feature on PSC2 outputs. See "PSC2 Outputs" on page 129. When Output Matrix is used, the PSC n Output Polarity POPn has no action on the outputs.
12.25.7
PSC 2 Extended Configuration Register - PCNFE2
Bit Read/Write Initial Value 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
PASDLKn2 PASDLKn1 PASDLKn0 PBFMn1
PELEVnA1 PELEVnB1 PISELnA1 PISELnB1 PCNFE2
The PSC n Extended Configuration Register is used to configure the running mode of the PSC * Bit 7, 6, 5- PASDLKn(2:0): Analog Synchronization Output Delay or Input Blanking select Defines the modes for Analog signal synchronization delay or Input Blanking.
Table 12-14.
PASDLKn2 0 0 0 0
Analog signal synchronization or Input Blanking Mode Selection
PASDLKn1 0 0 1 1 PASDLKn0 0 1 0 1 Description No Analog signal synchronization delay, no Input Blanking No Analog signal synchronization delay , Input Blanking using PSC clock, started on PSC end of cycle No Analog signal synchronization delay , Input Blanking using PSC clock, started on OCR SA event No Analog signal synchronization delay , Input Blanking using PSC clock, started on OCR SB event
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Table 12-14.
PASDLKn2 1 1 1 1
Analog signal synchronization or Input Blanking Mode Selection
PASDLKn1 0 0 1 1 PASDLKn0 0 1 0 1 Description Analog signal synchronization delay with PSC clock, no Input Blanking Analog signal synchronization delay with PSC clock /2 , no Input Blanking Analog signal synchronization delay with PSC clock /4 , no Input Blanking Analog signal synchronization delay with PSC clock /8, no Input Blanking
* Bit 4- PBFMn1: Balance Flank Width Modulation, bit 1 Defines the Flank Width Modulation, together with PBFMn0 bit in PCTLn register. Table 12-15.
PBFMn1 0 0 1 1 1.
Flank Width Mode Selection
PBFMn0 0 1 0 1 Description Flank Width Modulation operates on RB (On-Time 1 only). Flank Width Modulation operates on RB + RA (On-Time 0 and On-Time 1). Flank Width Modulation operates on SB (Dead-Time 1 only) (1). Flank Width Modulation operates on SB +SA (Dead-Time 0 and DeadTime 1).
Note: In one ramp mode, changing SA or SA+SB also affect On-Time ; see PSCn0 & PSCn1 Basic Waveforms in One Ramp mode
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* Bit 3- PELEVnA1: PSC n Input Select for part A Together with PELEVnA0, defines active edge or level on PSC part A. Table 12-16.
PELEVnA1 0 0 1 1
PSC edge & level input Selection
PELEVnA0 0 1 0 1 Description The falling edge or low level of selected input generates the significative event for retrigger or fault function The rising edge or high level of selected input generates the significative event for retrigger or fault function The toggle of selected input generates the significative event for retrigger or fault function Reserved
* Bit 2- PELEVnB1: PSC n Input Select for part B Together with PELEVnB0, defines active edge or level on PSC part B. Table 12-17.
PELEVnB1 0 0 1 1
PSC edge & level input Selection
PELEVnB0 0 1 0 1 Description The falling edge or low level of selected input generates the significative event for retrigger or fault function The rising edge or high level of selected input generates the significative event for retrigger or fault function The toggle of selected input generates the significative event for retrigger or fault function Reserved
* Bit 1- PISELnA1: PSC n Input Select for part A Together with PISELnA0, defines active signal on PSC part A. Table 12-18.
PISELnA1 0 0 1 1
PSC trigger & fault input Selection
PISELnA0 0 1 0 1 Description PSCINn First analog comparator output PSCINnA Second analog comparator output
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* Bit 0- PISELnB1: PSC n Input Select for part B Together with PISELnB0, defines active signal on PSC part B. Table 12-19.
PISELnB1 0 0 1 1
PSC trigger & fault input Selection
PISELnB0 0 1 0 1 Description PSCINn First analog comparator output PSCINnA Second analog comparator output
12.25.8
Analog Synchronization Delay Register - PASDLYn
Bit Read/Write Initial Value 7 W 0 6 W 0 5 W 0 4 W 0 3 W 0 2 W 0 1 W 0 0 PASDLYn W 0
PASDLYn[7:0]
The Analog Synchronization Delay Register store an 8 bit delay used: * For the input signal blanking. See Section "PSC Inputs", page 113 * For shifting the PSCOUTnx edges and the PSCnASY signal. See Section "Analog Synchronization", page 130 See also the bit definition Section "Bit 7, 6, 5- PASDLKn(2:0): Analog Synchronization Output Delay or Input Blanking select", page 136 and Section "Bit 5:4 - PSYNCn1:0: Synchronization Out for ADC Selection", page 133
12.25.9
PSC 2 Control Register - PCTL2
Bit Read/Write Initial Value 7 PPRE21 R/W 0 6 PPRE20 R/W 0 5 PBFM20 R/W 0 4 PAOC2B R/W 0 3 PAOC2A R/W 0 2 PARUN2 R/W 0 1 PCCYC2 R/W 0 0 PRUN2 R/W 0 PCTL2
* Bit 7:6 - PPREn1:0 : PSC n Prescaler Select This two bits select the PSC input clock division factor.All generated waveform will be modified by this factor. Table 12-20.
PPREn1 0
PSC n Prescaler Selection
PPREn0 0 Description No divider on PSC input clock
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Table 12-20.
PPREn1 0 1 1
PSC n Prescaler Selection
PPREn0 1 0 1 Description Divide the PSC input clock by 4 Divide the PSC input clock by 16 Divide the PSC clock by 64
* Bit 5 - PBFMn0 : Balance Flank Width Modulation bit 0 Defines the Flank Width Modulation, together with PBFMn1 bit in PCNFEn register. See Table 12-15 on page 137 * Bit 4 - PAOCnB : PSC n Asynchronous Output Control B When this bit is set, Fault input selected to block B can act directly to PSCOUTn1 and PSCOUT23 outputs. See Section "PSC Clock Sources", page 132. * Bit 3 - PAOCnA : PSC n Asynchronous Output Control A When this bit is set, Fault input selected to block A can act directly to PSCOUTn0 and PSCOUT22 outputs. See Section "PSC Clock Sources", page 132. * Bit 2 - PARUNn : PSC n Autorun When this bit is set, the PSC n starts with PSCn-1. That means that PSC n starts : * when PRUNn bit in PCTLn register is set, * or when PARUNn bit in PCTLn is set and PRUNn-1 bit in PCTLn-1 register is set (or PARUN0 bit and PRUN0). * Bit 1 - PCCYCn : PSC n Complete Cycle When this bit is set, the PSC n completes the entire waveform cycle before halt operation requested by clearing PRUNn. This bit is not relevant in slave mode (PARUNn = 1). * Bit 0 - PRUNn : PSC n Run Writing this bit to one starts the PSC n. When set, this bit prevails over PARUNn bit.
12.25.10
PSC n Input A Control Register - PFRCnA
Bit Read/Write Initial Value 7 PCAEnA R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
PISELnA0 PELEVnA0 PFLTEnA
PRFMnA3 PRFMnA2 PRFMnA1 PRFMnA0 PFRCnA
12.25.11
PSC n Input B Control Register - PFRCnB
Bit Read/Write Initial Value 7 PCAEnB R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
PISELnB0 PELEVnB0 PFLTEnB
PRFMnB3 PRFMnB2 PRFMnB1 PRFMnB0 PFRCnB
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The Input Control Registers are used to configure the 2 PSC's Retrigger/Fault block A & B. The 2 blocks are identical, so they are configured on the same way. * Bit 7 - PCAEnx : PSC n Capture Enable Input Part x Writing this bit to one enables the capture function when external event occurs on input selected as input for Part x (see PISELnx1:0 bit in the same register). * Bit 6 - PISELnx0 : PSC n Input Select for Part x Together with PISELnx1 in PCNFEn register, defines active signal on PSC module A. See Table 12-18 on page 138 and Table 12-19 on page 139 * Bit 5 -PELEVnx0 : PSC n Edge Level Selector of Input Part x Together with PELEVnx1 n PCNFEn register, defines active edge & level on PSC part x ; See Table 1216 on page 138 and Table 12-17 on page 138 * Bit 4 - PFLTEnx : PSC n Filter Enable on Input Part x Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the retrigger pin is filtered. The filter function requires four successive equal valued samples of the retrigger pin for changing its output. The Input Capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. * Bit 3:0 - PRFMnx3:0: PSC n Fault Mode These four bits define the mode of operation of the Fault or Retrigger functions. (see PSC Functional Specification for more explanations)
Table 12-21.
PRFMnx3:0 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b
Level Sensitivity and Fault Mode Operation
Description
No action, PSC Input is ignored
PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait
PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active PSC Input Mode 4: Deactivate outputs without changing timing. PSC Input Mode 5: Stop signal and Insert Dead-Time PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. PSC Input Mode 7: Halt PSC and Wait for Software Action PSC Input Mode 8: Edge Retrigger PSC PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC
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Table 12-21.
PRFMnx3:0 1010b 1011b 1100b 1101b 1110b 1111b
Level Sensitivity and Fault Mode Operation
Description
Reserved (do not use)
PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate Output Reserved (do not use)
12.25.12
PSC 2 Input Capture Register - PICR2H and PICR2L
Bit 7 PCST2 PICR2[7:0] Read/Write Initial Value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 6 - 5 - 4 - 3 PICR2[11:8] 2 1 0 PICR2H PICR2L
* Bit 7 - PCSTn : PSC Capture Software Trig bit Set this bit to trigger off a capture of the PSC counter. When reading, if this bit is set it means that the capture operation was triggered by PCSTn setting otherwise it means that the capture operation was triggered by a PSC input. The Input Capture is updated with the PSC counter value each time an event occurs on the enabled PSC input pin (or optionally on the Analog Comparator output) if the capture function is enabled (bit PCAEnx in PFRCnx register is set). The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit or 12-bit registers.
12.26 PSC2 Specific Register
12.26.1
PSC 2 Output Matrix - POM2
Bit Read/Write Initial Value 7 POMV2B3 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
POMV2B2 POMV2B1 POMV2B0 POMV2A3 POMV2A2 POMV2A1 POMV2A0 POM2
* Bit 7 - POMV2B3: Output Matrix Output B Ramp 3 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 3 * Bit 6 - POMV2B2: Output Matrix Output B Ramp 2 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 2 * Bit 5 - POMV2B1: Output Matrix Output B Ramp 1 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 1
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* Bit 4 - POMV2B0: Output Matrix Output B Ramp 0 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 0 * Bit 3 - POMV2A3: Output Matrix Output A Ramp 3 This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 3 * Bit 2 - POMV2A2: Output Matrix Output A Ramp 2 This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 2 * Bit 1 - POMV2A1: Output Matrix Output A Ramp 1 This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 1 * Bit 0 - POMV2A0: Output Matrix Output A Ramp 0 This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 0
12.26.2
PSC2 Interrupt Mask Register - PIM2
Bit Read/Write Initial Value 7 R 0 6 R 0 5 PSEIE2 R/W 0 4 PEVE2B R/W 0 3 PEVE2A R/W 0 2 R 0 1 PEOEPE2 R/W 0 0 PEOPE2 R/W 0 PIM2
* Bit 5 - PSEIEn : PSC n Synchro Error Interrupt Enable When this bit is set, the PSEIn bit (if set) generate an interrupt. * Bit 4 - PEVEnB : PSC n External Event B Interrupt Enable When this bit is set, an external event which can generates a capture from Retrigger/Fault block B generates also an interrupt. * Bit 3 - PEVEnA : PSC n External Event A Interrupt Enable When this bit is set, an external event which can generates a capture from Retrigger/Fault block A generates also an interrupt. * Bit 1- PEOEPEn : PSC n End Of Enhanced Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSC reaches the end of the 15th PSC cycle. This allows to update the PSC values in the interrupt routine and to start a new enhanced cycle with the new values at the next PSC cycle end. * Bit 0 - PEOPEn : PSC n End Of Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
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12.26.3
PSC2 Interrupt Flag Register - PIFR2
Bit Read/Write Initial Value 7 POAC2B R 0 6 POAC2A R 0 5 PSEI2 R/W 0 4 PEV2B R/W 0 3 PEV2A R/W 0 2 PRN21 R 0 1 PRN20 R 0 0 PEOP2 R/W 0 PIFR2
* Bit 7 - POACnB : PSC n Output B Activity This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0. Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSC output doesn't change due to a frozen external input signal. * Bit 6 - POACnA : PSC n Output A Activity This bit is set by hardware each time the output PSCOUTn0 changes from 0 to 1 or from 1 to 0. Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSC output doesn't change due to a frozen external input signal. * Bit 5 - PSEIn : PSC n Synchro Error Interrupt This bit is set by hardware when the update (or end of PSC cycle) of the PSCn configured in auto run (PARUNn = 1) does not occur at the same time than the PSCn-1 which has generated the input run signal. (For PSC0, PSCn-1 is PSC2). Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSC doesn't run at the same speed or with the same phase than the PSC master. * Bit 4 - PEVnB : PSC n External Event B Interrupt This bit is set by hardware when an external event which can generates a capture or a retrigger from Retrigger/Fault block B occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVEnB bit = 0). * Bit 3 - PEVnA : PSC n External Event A Interrupt This bit is set by hardware when an external event which can generates a capture or a retrigger from Retrigger/Fault block A occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVEnA bit = 0). * Bit 2:1 - PRNn1:0 : PSC n Ramp Number Memorization of the ramp number when the last PEVnA or PEVnB occurred .
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Table 12-22.
PRNn1 0 0 1 1
PSC n Ramp Number Description
PRNn0 0 1 0 1 Description The last event which has generated an interrupt occurred during ramp 1 The last event which has generated an interrupt occurred during ramp 2 The last event which has generated an interrupt occurred during ramp 3 The last event which has generated an interrupt occurred during ramp 4
* Bit 0 - PEOPn: End Of PSC n Interrupt This bit is set by hardware when PSC n achieves its whole cycle. Must be cleared by software by writing a one to its location. 12.26.4 PSC Output Behavior During Reset For external component safety reason, the state of PSC outputs during Reset can be programmed by fuses PSCRV, PSCRRB & PSC2RB. These fuses are located in the Extended Fuse Byte :
Table 12-23.
Extended Low Fuse Byte
Bit No 7 6 5 4 3 2 1 0 Description PSC2 Reset Behavior PSC2 Reset Behavior for OUT22 & 23 PSC Reduced Reset Behavior PSCOUT & PSCOUTR Reset Value PSC & PSCR Inputs Reset Behavior Brown-out Detector trigger level Brown-out Detector trigger level Brown-out Detector trigger level Default Value 1 1 1 1 1 1 (unprogrammed) 0 (programmed) 1 (unprogrammed)
Extended Fuse Byte PSC2RB PSC2RBA PSCRRB PSCRV PSCINRB BODLEVEL2(1) BODLEVEL1
(1)
BODLEVEL0(1) Notes:
1. See Table 7-2 on page 52 for BODLEVEL Fuse decoding
PSCRV gives the state low or high which will be forced on PSC outputs selected by PSC0RB & PSC2RB fuses. If PSCRV fuse equals 0 (programmed), the selected PSC outputs will be forced to low state. If PSCRV fuse equals 1 (unprogrammed), the selected PSC outputs will be forced to high state. If PSCRRB fuse equals 1 (unprogrammed), PSCOUTR0 & PSCOUTR1 keep a standard port behavior. If PSC0RB fuse equals 0 (programmed), PSCOUTR0 & PSCOUTR1 are forced at reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUTR0 & PSCOUTR1 keep the forced state until PSOC0 register is written. If PSC2RB fuse equals 1 (unprogrammed), PSCOUT20 & PSCOUT21 keep a standard port behavior. If PSC2RB fuse equals 0 (programmed), PSCOUT20 & PSCOUT21 are forced at reset to low level or high
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level according to PSCRV fuse bit. In this second case, PSCOUT20 & PSCOUT21 keep the forced state until PSOC2 register is written. If PSC2RBA fuse equals 1 (unprogrammed), PSCOUT22 & PSCOUT23 keep a standard port behavior. If PSC2RBA fuse equals 0 (programmed), PSCOUT22 & PSCOUT23 are forced at reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUT22 & PSCOUT23 keep the forced state until PSOC2 register is written. 12.26.5 PSC Input Behavior During Reset For power consumption under reset reason, the state of PSC & PSCR inputs during Reset can be programmed by fuse PSCINRB. If PSCINRB fuse equals 1 (unprogrammed), PSC & PSCR input keep a standard port behavior. If PSCINRB fuse equals 0 (programmed), PSC & PSCR input pull-up are forced while the reset is active. Affected pins are PSCIN2, PSCINr, PSCIN2A, PSCINrA. To prevent any conflict on PD1, this fuse has no effect on PSCINrB.
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13. Reduced Power Stage Controller - (PSCR)
The Reduced Power Stage Controller is a high performance waveform controller.
13.1
Features
* * * * * * * * *
PWM waveform generation function (2 complementary programmable outputs) Dead time control Standard mode up to 12 bit resolution Enhanced resolution up to 16 bits Frequency up to 64 Mhz Conditional Waveform on External Events (Zero Crossing, Current Sensing ...) ADC synchronization Overload protection function Abnormality protection function, emergency input to force all outputs to high impedance or in inactive state (fuse configurable) * Fast emergency stop by hardware
13.2
Overview
Many register and bit references in this section are written in general form. * A lower case "r" (or "n" replaces the PSC number, in this case 0. However, when using the register or bit defines in a program, the precise form must be used, i.e., PSOC0 for accessing PSCR 0 Synchro and Output Configuration register and so on. * A lower case "x" replaces the PSCR part , in this case A or B. However, when using the register or bit defines in a program, the precise form must be used, i.e., PFRC0A for accessing PSCR 0 Fault/Retrigger A Control register and so on. The purpose of a Power Stage Controller (PSC) is to control power modules on a board. It has two outputs . These outputs can be used in various ways: * "Two Outputs" to drive a half bridge (lighting, ...) * "One Output" to drive single power transistor (DC/DC converter, PFC, ...) The PSCR has two inputs the purpose of which is to provide means to act directly on the generated waveforms: * Current sensing regulation * Zero crossing retriggering * Demagnetization retriggering * Fault input
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13.3
PSCR Description
Figure 13-1. Power Stage Controller Block Diagram
PSCR Counter
=
OCRrRB
Waveform Gererator B
PSCOUTr1
= DATABUS
OCRrSB
PSC Input Module B
PSCr Input B
Part B
=
OCRrRA
PSC Input Module A
PSCr Input A
=
OCRrSA
Waveform Gererator A
PSCOUTr0
Part A
PICRr
PCNFr PCTLr
PFRCrB PFRCrA PSOCr
The principle of the PSCR is based on the use of a counter (PSCR counter). This counter is able to count up and count down from and to values stored in registers according to the selected running mode. The PSCR is seen as two symmetrical entities. One part named part A which generates the output PSCOUTr0 and the second one named part B which generates the PSCOUTr1 output. Each part A or B has its own PSCR Input Module to manage selected input.
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13.3.1 Output Polarity The polarity "active high" or "active low" of the PSCR outputs is programmable. All the timing diagrams in the following examples are given in the "active high" polarity.
13.4
Signal Description
Figure 13-2. PSCR External Block View
CLK PLL CLK I/O
OCRrR B[11:0] OCRrSB[11:0] OCRrR A[11:0] OCRrSA[11:0]
12 12 12 12
PSCOUT r0 PSCOUT r1
PICRr[11:0] IRQ PSC r
12
3
PSCINr Aralog Comparator Output
PSCrASY
13.4.1
Input Description Table 13-1.
Name OCRrRB[11 :0] OCRrSB[11: 0] OCRrRA[11 :0]
Internal Inputs Description
Compare Value which Reset Signal on Part B (PSCOUTr1) Compare Value which Set Signal on Part B (PSCOUTr1) Compare Value which Reset Signal on Part A (PSCOUTr0)
Type Width
Register 12 bits Register 12 bits Register 12 bits
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Name OCRrSA[11 :0] CLK I/O CLK PLL
Description
Compare Value which Set Signal on Part A (PSCOUTr0) Clock Input from I/O clock Clock Input from PLL
Type Width
Register 12 bits Signal Signal
Table 13-2.
Name PSCINr from Analog Comparator PSCINrA PSCINrB
Block Inputs Description
Input 0 used for Retrigger or Fault functions Input 1 used for Retrigger or Fault functions Input 2 used for Retrigger or Fault functions Input 3 used for Retrigger or Fault functions
Type Width
Signal Signal Signal Signal
13.4.2
Output Description Table 13-3.
Name PSCOUTr0 PSCOUTr1
Block Outputs Description
PSCR Output 0 (from part A of PSC) PSCR Output 1 (from part B of PSC)
Type Width
Signal Signal
Table 13-4.
Name PICRr [11:0] IRQPSCr PSCrASY
Internal Outputs Description
PSCR Input Capture Register Counter value at retriggering event PSCR Interrupt Request : three sources, overflow, fault, and input capture ADC Synchronization (+ Amplifier Syncho. )(2)
Type Width
Register 12 bits Signal Signal
2. See "Analog Synchronization" on page 169.
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13.5
13.5.1
Functional Description
Waveform Cycles The waveform generated by PSCR can be described as a sequence of two waveforms. The first waveform is relative to PSCOUTr0 output and part A of PSC. The part of this waveform is subcycle A in the following figure. The second waveform is relative to PSCOUTr1 output and part B of PSC. The part of this waveform is sub-cycle B in the following figure. The complete waveform is ended with the end of sub-cycle B. It means at the end of waveform B. Figure 13-3. Cycle Presentation in 1, 2 & 4 Ramp Mode
PSC Cycle Sub-Cycle A Sub-Cycle B
4 Ramp Mode Ramp A0 Ramp A1 Ramp B0 Ramp B1
2 Ramp Mode
Ramp A
Ramp B
1 Ramp Mode
UPDATE
Ramps illustrate the output of the PSCR counter included in the waveform generators. Centered Mode is like a one ramp mode which count down up and down. Notice that the update of a new set of values is done regardless of ramp Mode at the top of the last ramp. 13.5.2 Running Mode Description Waveforms and length of output signals are determined by Time Parameters (DT0, OT0, DT1, OT1) and by the running mode. Three modes are possible : - Four Ramp mode - Two Ramp mode - One Ramp mode
The active time of PSCOUTn0 is given by the OT0 value. The active time of PSCOUTn1 is given by the OT1 value. Both of them are 12 bit values. Thanks to DT0 & DT1 to adjust the dead time between PSCOUTn0 and PSCOUTn1 active signals.
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The waveform frequency is defined by the following equation: f CLK_PSCn 1 f PSCn = ----------------------------- = -------------------------------------------------------------------PSCnCycle ( OT0 + OT1 + DT0 + DT1 )
13.5.2.1
Four Ramp Mode In Four Ramp mode, each time in a cycle has its own definition Figure 13-4. PSCr0 & PSCr1 Basic Waveforms in Four Ramp mode
OCRnRA OCRnSB
0
PSC Counter OCRnSA
0
OCRnRB
On-Time 0
On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 0 PSC Cycle
Dead-Time 1
The input clock of PSCR is given by CLKPSC. PSCOUTr0 and PSCOUTr1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and Dead-Time 1 values with : On-Time 0 = OCRrRAH/L * 1/Fclkpsc On-Time 1 = OCRrRBH/L * 1/Fclkpsc Dead-Time 0 = (OCRrSAH/L + 2) * 1/Fclkpsc Dead-Time 1 = (OCRrSBH/L + 2) * 1/Fclkpsc
Note: Minimal value for Dead-Time 0 and Dead-Time 1 = 2 * 1/Fclkpsc
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13.5.2.2 Two Ramp Mode In Two Ramp mode, the whole cycle is divided in two moments One moment for PSCr0 description with OT0 which gives the time of the whole moment One moment for PSCr1 description with OT1 which gives the time of the whole moment Figure 13-5.
PSC Counter OCRnSA
0 0
PSCr0 & PSCr1 Basic Waveforms in Two Ramp mode
OCRnRA OCRnSB OCRnRB
On-Time 0
On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 0 PSC Cycle
Dead-Time 1
PSCOUTr0 and PSCOUTr1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and Dead-Time 1 values with : On-Time 0 = (OCRrRAH/L - OCRrSAH/L) * 1/Fclkpsc On-Time 1 = (OCRrRBH/L - OCRrSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRrSAH/L + 1) * 1/Fclkpsc Dead-Time 1 = (OCRrSBH/L + 1) * 1/Fclkpsc
Note: Minimal value for Dead-Time 0 and Dead-Time 1 = 1/Fclkpsc
13.5.2.3
One Ramp Mode In One Ramp mode, PSCOUTr0 and PSCOUTr1 outputs can overlap each other.
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Figure 13-6.
PSCr0 & PSCr1 Basic Waveforms in One Ramp mode
OCRnRB OCRnSB OCRnRA
PSC Counter OCRnSA
0
On-Time 0
On-Time 1
PSCOUTn0
PSCOUTn1
Dead-Time 0 PSC Cycle
Dead-Time 1
On-Time 0 = (OCRrRAH/L - OCRrSAH/L) * 1/Fclkpsc On-Time 1 = (OCRrRBH/L - OCRrSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRrSAH/L + 1) * 1/Fclkpsc Dead-Time 1 = (OCRrSBH/L - OCRrRAH/L) * 1/Fclkpsc
Note: Minimal value for Dead-Time 0 = 1/Fclkpsc
13.5.3
Fifty Percent Waveform Configuration When PSCOUTr0 and PSCOUTr1 have the same characteristics, it's possible to configure the PSCR in a Fifty Percent mode. When the PSCR is in this configuration, it duplicates the OCRrSBH/L and OCRrRBH/L registers in OCRrSAH/L and OCRrRAH/L registers. So it is not necessary to program OCRrSAH/L and OCRrRAH/L registers.
13.6
Update of Values
The update of PSCR waveform registers are done in the following way: * * * Immediately when the PSC is stopped At the PSC end of cycle when the PSC is running At the PSC end of cycle following the required condition when LOCK or AUTOLOCK modes are used. To avoid asynchronous and incoherent values in a cycle, if an update of one of several values is necessary, all values are updated at the same time at the end of the cycle by the PSC. The new set of values is calculated by software and the update is initiated by software.
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Figure 13-7.
Software
Update at the end of complete PSCR cycle.
Regulation Loop Calculation Writting in PSC Registers Request for an Update
Cycle With Set i PSC
Cycle With Set i
Cycle With Set i
Cycle With Set i Cycle With Set j
End of Cycle
The software can stop the cycle before the end to update the values and restart a new PSCR cycle. 13.6.1 Value Update Synchronization New timing values or PSCR output configuration can be written during the PSCR cycle. Thanks to LOCK and AUTOLOCK configuration bits, the new whole set of values can be taken into account with the following conditions: * When AUTOLOCK configuration is selected, the update of the PSCR internal registers will be done at the end of the PSCR cycle following a write in the Output Compare Register RB. The AUTOLOCK configuration bit is taken into account at the end of the first PSCR cycle. * When LOCK configuration bit is set, there is no update. The update of the PSCR internal registers will be done at the end of the PSCR cycle if the LOCK bit is released to zero. The registers which update is synchronized thanks to LOCK and AUTOLOCK are OCRrSAH/L, OCRrRAH/L, OCRrSBH/L, OCRrRBH/L and PSOCr. PISELrA1 and PISELrB1 bits of PSOCr are immediatly updated in order to behave as PISELrA0 and PISELrB0. See these register's description starting on page 172. When set, AUTOLOCK configuration bit prevails over LOCK configuration bit. See "PSCR Configuration Register - PCNF0" on page 173.
13.7
Enhanced resolution
The PSCR includes the same resolution enhancement as in PSC. Please see Section "Enhanced Resolution", page 110 for the description of this feature.
13.8
PSCR Inputs
Each part A or B of PSCR has its own system to take into account one PSCR input. According to PSCR Input A/B Control Register (see description 13.23.8page 175), PSCrIN0/1 input can act has a Retrigger or Fault input. This system A or B is also configured by this PSCR Input A/B Control Register (PFRCrA/B).
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Figure 13-8.
PSCR Input Module
PAO CrA (PA OCrB)
PSCINr AC1 Analog O: Comparator Output PSCINrA
0
0 0
0 1
1 0
PSCR Input A (PSCR Input B)
Digital Filter
1
CLK PSC PSCINrB 1 1 PELE rA / V (PELE rB V) PISELrA1 PISELrA0 (PISELrB1) (PISELrB0) PCAErA (PCAErB) PRFM rA3:0 (PRFM rB3:0)
PFLTErA (PFLTErB)
2 4 CLK PSC
Input Processing (retriggering ...)
PSC Cre o (Counter, Waveform Generator, ...) CLK PSC
Output Control
PSCOUT r0 (PSCOUT r1)
13.8.1
PSCR Retrigger Behavior versus PSCR running modes In two ramp or four ramp mode, Retrigger Inputs A or B cause the end of the corresponding cycle A or B and the beginning of the following cycle B or A. In one ramp mode, Retrigger Inputs A or B reset the current PSCR counting to zero.
13.8.2
Retrigger PSCOUTr0 On External Event PSCOUTr0 output can be reset before end of On-Time 0 on the change on PSCr Input A. PSCr Input A can be configured to do not act or to act on level or edge modes. The polarity of PSCr Input A is configurable thanks to a sense control block. PSCr Input A can be the Output of the analog comparator or the PSCINr input. As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.
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Figure 13-9. PSCOUTr0 retriggered by PSCr Input A (Edge Retriggering)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input A (falling edge)
PSCn Input A (rising edge)
Dead-Time 0
Dead-Time 1
Note:
This example is given in "Input Mode 8" in "2 or 4 ramp mode" See Figure 13-25. for details.
Figure 13-10. PSCOUTr0 retriggered by PSCr Input A (Level Acting)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input A (high level)
PSCn Input A (low level)
Dead-Time 0
Dead-Time 1
Note:
This example is given in "Input Mode 1" in "2 or 4 ramp mode" See Figure 13-14. for details.
13.8.3
Retrigger PSCOUTr1 On External Event PSCOUTr1 output can be reset before end of On-Time 1 on the change on PSCr Input B. The polarity of PSCr Input B is configurable thanks to a sense control block. PSCr Input B can be configured to do not act or to act on level or edge modes. PSCr Input B can be the Output of the analog comparator or the PSCINr input. As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.
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Figure 13-11. PSCOUTr1 retriggered by PSCr Input B (Edge Retriggering)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input B (falling edge)
PSCn Input B (rising edge) Dead-Time 0 Dead-Time 1 Dead-Time 0
Note:
This example is given in "Input Mode 8" in "2 or 4 ramp mode" See Figure 13-25. for details.
Figure 13-12. PSCOUTr1 retriggered by PSCr Input B (Level Acting)
On-Time 0 On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input B (high level)
PSCn Input B (low level) Dead-Time 0 Dead-Time 1 Dead-Time 0
Note:
This example is given in "Input Mode 1" in "2 or 4 ramp mode" See Figure 13-14. for details.
13.8.3.1
Burst Generation
Note:
On level mode, it's possible to use PSCR to generate burst by using Input Mode 3 or Mode 4 (See
Figure 13-18. and Figure 13-19. for details.)
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Figure 13-13. Burst Generation
OFF BURST
PSCOUTn0
PSCOUTn1
PSCn Input A (high level)
PSCn Input A (low level)
13.8.4
PSCR Input Configuration The PSCR Input Configuration is done by programming bits in configuration registers. Filter Enable If the "Filter Enable" bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal. The disable of this function is mainly needed for prescaled PSCR clock sources, where the noise cancellation gives too high latency. Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSCR clock to deactivate the outputs (emergency protection of external component). Likewise when used as fault input, PSCr Input A or Input B have to go through PSCR to act on PSCOUTr0/1/2/3 output. This way needs that CLKPSCR is running. So thanks to PSCR Asynchronous Output Control bit (PAOCrA/B), PSCrIN0/1 input can deactivate directly the PSCR output. Notice that in this case, input is still taken into account as usually by Input Module System as soon as CLKPSCR is running. PSCR Input Flittering
CLKPSC
13.8.4.1
Digital Filter 4 x CLK PSC
PSCn Input A or B
PSC Input Module X
Ouput Stage
PSCOUTnX PIN
13.8.4.2
Signal Polarity One can select the active edge (edge modes) or the active level (level modes) See PELEV0x bit description in Section "PSCR Input A Control Register - PFRC0A", page 17513.23.8.
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If PELEV0x bit set, the significant edge of PSCr Input A or B is rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low - In 2- or 4-ramp mode, PSCr Input A is taken into account only during Dead-Time0 and On-Time0 period (respectively Dead-Time1 and On-Time1 for PSCr Input B). - In 1-ramp-mode PSCR Input A or PSCR Input B act on the whole ramp. 13.8.4.3 Input Mode Operation Thanks to 4 configuration bits (PRFM3:0), it's possible to define the mode of the PSCR input. All
Table 13-5.
PSCR Input Mode Operation
Description
PRFM3:0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b
PSCr Input has no action on PSCR output 13.9See "PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait" on page 161. See "PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait" on page 162. See "PSCR Input Mode 3: Stop signal, Execute Opposite while Fault active" on page 163. See "PSCR Input Mode 4: Deactivate outputs without changing timing." on page 164. See "PSCR Input Mode 5: Stop signal and Insert Dead-Time" on page 164. See "PSCR Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait." on page 165. See "PSCR Input Mode 7: Halt PSCR and Wait for Software Action" on page 165. See "PSCR Input Mode 8: Edge Retrigger PSC" on page 166. See "PSCR Input Mode 9: Fixed Frequency Edge Retrigger PSC" on page 167. Reserved : Do not use
See "PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate Output" on page 168. Reserved : Do not use
Notice: All following examples are given with rising edge or high level active inputs.
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13.9 PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait
Figure 13-14. PSCr behavior versus PSCr Input A in Fault Mode 1
DT0 PSCOUTn0 PSCOUTn1 OT0 DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSCR Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSCR Input A event occurs, PSCR releases PSCOUTr0, waits for PSCR Input A inactive state and then jumps and executes DT1 plus OT1.
Figure 13-15. PSCr behavior versus PSCr Input B in Fault Mode 1
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSCR Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0. When PSCR Input B event occurs, PSCR releases PSCOUTr1, waits for PSCR Input B inactive state and then jumps and executes DT0 plus OT0.
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13.10 PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait
Figure 13-16. PSCr behavior versus PSCr Input A in Fault Mode 2
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0 OT0 DT1 OT1
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSCR Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSCr Input A event occurs, PSCR releases PSCOUTr0, jumps and executes DT1 plus OT1 and then waits for PSCR Input A inactive state. Even if PSCR Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always completely executed. Figure 13-17. PSCr behavior versus PSCr Input B in Fault Mode 2
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSCR Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0. When PSCR Input B event occurs, PSCR releases PSCOUTr1, jumps and executes DT0 plus OT0 and then waits for PSCR Input B inactive state. Even if PSCR Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always completely executed.
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13.11 PSCR Input Mode 3: Stop signal, Execute Opposite while Fault active
Figure 13-18. PSCr behavior versus PSCr Input A in Mode 3
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0 OT0 DT1 OT1
DT1 OT1
DT1 OT1
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSCR Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and OT1. When PSCR Input A event occurs, PSCR releases PSCOUTr0, jumps and executes DT1 plus OT1 plus DT0 while PSCR Input A is in active state. Even if PSCR Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always completely executed. Figure 13-19. PSCr behavior versus PSCr Input B in Mode 3
DT0 PSCOUTn0 PSCOUTn1 OT0 DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT0
OT0
DT0
OT0
DT1
OT1
PSC Input A PSC Input B
PSCR Input B is taken into account during DT1 and OT1 only. It has no effect during DT0 and OT0. When PSCR Input B event occurs, PSCR releases PSCOUTR1, jumps and executes DT0 plus OT0 plus DT1 while PSCR Input B is in active state. Even if PSCR Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always completely executed.
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13.12 PSCR Input Mode 4: Deactivate outputs without changing timing.
Figure 13-20. PSCR behavior versus PSCr Input A or Input B in Mode 4
DT0 PSCOUTn0 PSCOUTn1 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCn Input A or PSCn Input B
Figure 13-21. PSCR behavior versus PSCr Input A or Input B in Fault Mode 4
DT0 PSCOUTn0 PSCOUTn1 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCn Input A or PSCn Input B
PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
13.13 PSCR Input Mode 5: Stop signal and Insert Dead-Time
Figure 13-22. PSCR behavior versus PSCr Input A in Fault Mode 5
DT1 DT0 DT1 DT0
DT0 PSCOUTn0 PSCOUTn1 OT0 DT0 OT0
DT0
DT1 OT1
PSCn Input A or PSCn Input B
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DT1
DT1
OT1
DT0
OT0
DT1
OT1
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Used in Fault mode 5, PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
13.14 PSCR Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait.
Figure 13-23. PSCR behavior versus PSCr Input A in Fault Mode 6
DT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B OT0 DT0 OT0 DT0 OT0
DT1 OT1
DT1
OT1
DT1
OT1
Used in Fault mode 6, PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
13.15 PSCR Input Mode 7: Halt PSCR and Wait for Software Action
Figure 13-24. PSCR behavior versus PSCr Input A in Fault Mode 7
DT0 PSCOUTn0 PSCOUTn1 OT0 DT0 OT0 DT0 OT0
DT1
OT1
DT1
OT1
PSCn Input A or PSCn Input B Software Action (1)
Note:
1. Software action is the setting of the PRUNn bit in PCTLr register.
Used in Fault mode 7, PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
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13.16 PSCR Input Mode 8: Edge Retrigger PSC
Figure 13-25. PSCR behavior versus PSCr Input A in Mode 8
DT0 PSCOUTn0 PSCOUTn1 OT0 DT0 OT0 DT0 OT0
DT1
OT1
DT1
OT1
DT1
OT1
PSCn Input A
The output frequency is modulated by the occurrence of significative edge of retriggering input.
Figure 13-26. PSCR behavior versus PSCr Input B in Mode 8
DT0 PSCOUTn0 PSCOUTn1 OT0 DT0 OT0 DT0 OT0
DT1
OT1
DT1
OT1
DT1
OT1
PSCn Input B or PSCn Input B
The output frequency is modulated by the occurrence of significative edge of retriggering input. The retrigger event is taken into account only if it occurs during the corresponding On-Time. Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSCR doesn't jump to the opposite dead-time.
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13.17 PSCR Input Mode 9: Fixed Frequency Edge Retrigger PSC
Figure 13-27. PSCR behavior versus PSCr Input A in Mode 9
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSCn Input A
The output frequency is not modified by the occurrence of significative edge of retriggering input. Only the output is deactivated when significative edge on retriggering input occurs. Note: In this mode the output of the PSCR becomes active during the next ramp even if the Retrigger/Fault input is active. Only the significative edge of Retrigger/Fault input is taken into account.
Figure 13-28. PSCR behavior versus PSCr Input B in Mode 9
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSCn Input B
The retrigger event is taken into account only if it occurs during the corresponding On-Time.
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13.18 PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate Output
Figure 13-29. PSCR behavior versus PSCr Input A in Mode 14
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSCn Input A
The output frequency is not modified by the occurrence of significative edge of retriggering input.
Figure 13-30. PSCR behavior versus PSCr Input B in Mode 14
DT0 PSCOUTn0 PSCOUTn1
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
DT0
OT0
DT1
OT1
PSCn Input B
The output is deactivated while retriggering input is active. The output of the PSCR is set to an inactive state and the corresponding ramp is not aborted. The output stays in an inactive state while the Retrigger/Fault input is active. The PSCR runs at constant frequency.
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13.18.1 Available Input Mode according to Running Mode Some Input Modes are not consistent with some Running Modes. So the table below gives the input modes which are valid according to running modes. Table 13-6. Available Input Modes according to Running Modes
1 Ramp Mode Valid Do not use Do not use Valid Do not use Do not use Valid Valid Valid 2 Ramp Mode Valid Valid Valid Valid Valid Valid Valid Valid Valid 4 Ramp Mode Valid Valid Valid Valid Valid Valid Valid Valid Valid
Input Mode Number : 1 2 3 4 5 6 7 8 9 10 11
Do not use 12 13 14 15 Valid Do not use Valid Valid
13.18.2
Event Capture The PSCR can capture the value of time (PSCR counter) when a retrigger event or fault event occurs on PSCR inputs. This value can be read by software in PICRrH/L register.
13.18.3
Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the PICR1 Register before the next event occurs, the PICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the PICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
13.19 Analog Synchronization
PSCR generates a signal to synchronize the sample and hold; synchronization is mandatory for measurements.
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This signal can be selected between all falling or rising edge of PSCr0 or PSCr1 outputs.
13.20 Interrupt Handling
List of interrupt sources: * Counter reload (end of On Time 1) * PSCR Input event (active edge or at the beginning of level configured event)
13.21 PSC Clock Sources
PSCR must be able to generate high frequency with enhanced resolution. The PSCR has two clock inputs: * CLK PLL from the PLL * CLK I/O Figure 13-31. Clock selection
CLK
PLL 1 CK PRESCALER
CLK
CK/4
CK
CK/32
00
01
10
PCLKSELr
11
CK/256
I/O
0
PPREr1/0
CLK
PSCr
PCLKSELr bit in PSCR Configuration register (PCNFr) is used to select the clock source. PPREr1/0 bits in PSCR Control Register (PCTLr) are used to select the divide factor of the clock.
Table 13-7.
PCLKSELr 0 0 0 0 1 1 1 1
Output Clock versus Selection and Prescaler
PPREr1 0 0 1 1 0 0 1 1 PPREr0 0 1 0 1 0 1 0 1 CLKPSCr output CLK I/O CLK I/O / 4 CLK I/O / 32 CLK I/O / 256 CLK PLL CLK PLL / 4 CLK PLL / 32 CLK PLL / 256
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13.22 Interrupts
This section describes the specifics of the interrupt handling as performed in AT90PWM81. 13.22.1 List of Interrupt Vector The PSCR provides 3 interrupt vectors * PSC0EC (End of Cycle): When enabled and when a match with OCRrRB occurs * PSC0EEC (End of Enhanced Cycle): When enabled and when a match with OCRrRB occurs at the 15th enhanced cycle * PSC0CAPT (Capture Event): When enabled and one of the two following events occurs : retrigger, capture of the PSCR counter or Synchro Error. * See PSC0 Interrupt Mask Register page 177 and PSC0 Interrupt Flag Register page 178.
13.23 PSCR Register Definition
13.23.1
PSCR Synchro and Output Configuration - PSOC0
Bit Read/Write Initial Value 7 PISEL0A1 R/W 0 6 R/W 0 5 R/W 0 4 PSYNC00 R/W 0 3 R/W 0 2 POEN0B R/W 0 1 R/W 0 0 POEN0A R/W 0 PSOC0
PISEL0B1 PSYNC01
* Bit 7- PISEL0A1: PSC Input Select for part A Together with PISEL0A0, defines active signal on PSCR part A. Table 13-8.
PISEL0A1 0 0 1 1
PSC trigger & fault input Selection
PISEL0A0 0 1 0 1 Description PSCIN0 Analog comparator output PSCIN0A PSCIN0B
* Bit 6- PISEL0B1: PSCR Input Select for part B Together with PISEL0B0, defines active signal on PSCR part B. Table 13-9.
PISEL0B1 0 0 1 1
PSC trigger & fault input Selection
PISEL0B0 0 1 0 1 Description PSCIN0 Analog comparator output PSCIN0A PSCIN0B
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* Bit 5:4 - PSYNC01:0: Synchronization Out for ADC Selection) Select the polarity and signal source for generating a signal which will be sent to the ADC for synchronization. Table 13-10.
PSYNC01 0 0 1 1
Synchronization Source Description in One/Two/Four Ramp Modes
PSYNC00 0 1 0 1 Description Send signal on leading edge of PSCOUT00 (match with OCR0SA) Send signal on trailing edge of PSCOUT00 (match with OCR0RA or fault/retrigger on part A) Send signal on leading edge of PSCOUT01 (match with OCR0SB) Send signal on trailing edge of PSCOUT01 (match with OCR0RB or fault/retrigger on part B)
* Bit 3 - Reserved. * Bit 2 - POEN0B: PSCR OUT Part B Output Enable When this bit is clear, I/O pin affected to PSCOUT01 acts as a standard port. When this bit is set, I/O pin affected to PSCOUT01 is connected to the PSCR waveform generator B output and is set and clear according to the PSCR operation. * Bit 1 - Reserved * Bit 0 - POEN0A: PSCR OUT Part A Output Enable When this bit is clear, I/O pin affected to PSCOUT00 acts as a standard port. When this bit is set, I/O pin affected to PSCOUT00 is connected to the PSCR waveform generator A output and is set and clear according to the PSCR operation. 13.23.2 Output Compare SA Register - OCR0SAH and OCR0SAL
Bit 7 - Read/Write Initial Value W 0 6 - W 0 5 - W 0 4 - W 0 3 2 1 0 OCR0SAH OCR0SAL W 0 W 0 W 0 W 0
OCR0SA[11:8]
OCR0SA[7:0]
13.23.3
Output Compare RA Register - OCR0RAH and OCR0RAL
Bit 7 - Read/Write Initial Value W 0 6 - W 0 5 - W 0 4 - W 0 3 2 1 0 OCR0RAH OCR0RAL W 0 W 0 W 0 W 0
OCR0RA[11:8]
OCR0RA[7:0]
13.23.4
Output Compare SB Register - OCR0SBH and OCR0SBL
Bit 7 - Read/Write Initial Value W 0 6 - W 0 5 - W 0 4 - W 0 3 2 1 0 OCR0SBH OCR0SBL W 0 W 0 W 0 W 0
OCR0SB[11:8]
OCR0SB[7:0]
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13.23.5 Output Compare RB Register - OCR0RBH and OCR0RBL
Bit 7 6 5 4 3 2 1 0 OCR0RBH OCR0RBL W 0 W 0 W 0 W 0 W 0 W 0
OCR0RB[15:12] OCR0RB[7:0] Read/Write Initial Value W 0 W 0
OCR0RB[11:8]
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the PSCR counter value. A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the associated pin. The Output Compare Registers RB contains also a 4-bit value that is used for the flank width modulation. The Output Compare Registers are 12-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers.
13.23.6
PSCR Configuration Register - PCNF0
Bit Read/Write Initial Value 7 PFIFTY0 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 PCNF0 R/W 0 PCLKSEL0 -
PALOCK0 PLOCK0
PMODE01 PMODE00 POP0
* Bit 7 - PFIFTY0: PSCR Fifty Writing this bit to one, set the PSCR in a fifty percent mode where only OCR0RBH/L and OCR0SBH/L are used. They are duplicated in OCR0RAH/L and OCR0SAH/L during the update of OCR0RBH/L. This feature is useful to perform fifty percent waveforms. * Bit 6 - PALOCK0: PSCR Autolock When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and the PSCR Output Configuration PSOC0 can be written without disturbing the PSCR cycles. The update of the PSCR internal registers will be done at the end of the PSCR cycle if the Output Compare Register RB has been the last written. When set, this bit prevails over LOCK (bit 5) * Bit 5 - PLOCK0: PSCR Lock When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2 and the PSCR Output Configuration PSOC0 can be written without disturbing the PSCR cycles. The update of the PSCR internal registers will be done if the LOCK bit is released to zero. * Bit 4:3 - PMODE01: 0: PSCR Mode Select the mode of PSC.
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Table 13-11.
PMODE01 0 0 1 1
PSCR Mode Selection
PMODE00 0 1 0 1 Description One Ramp Mode Two Ramp Mode Four Ramp Mode Reserved
* Bit 2 - POP0: PSCR Output Polarity If this bit is cleared, the PSCR outputs are active Low. If this bit is set, the PSCR outputs are active High. * Bit 1 - PCLKSEL0: PSCR Input Clock Select This bit is used to select between CLKPF or CLKPS clocks. Set this bit to select the fast clock input (CLKPF). Clear this bit to select the slow clock input (CLKPS). * Bit 0 - Reserved
13.23.7
PSCR Control Register - PCTL0
Bit Read/Write Initial Value 7 PPRE01 R/W 0 6 PPRE00 R/W 0 5 PBFM01 R/W 0 4 PAOC0B R/W 0 3 PAOC0A R/W 0 2 PBFM00 R/W 0 1 PCCYC0 R/W 0 0 PRUN0 R/W 0 PCTL0
* Bit 7:6 - PPRE01:0 : PSCR Prescaler Select This two bits select the PSCR input clock division factor. All generated waveform will be modified by this factor. Table 13-12.
PPRE01 0 0 1 1
PSCR Prescaler Selection
PPRE00 0 1 0 1 Description No divider on PSCR input clock Divide the PSCR input clock by 4 Divide the PSCR input clock by 32 Divide the PSCR clock by 256
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* Bit 5- PBFM01: Balance Flank Width Modulation, bit 1 Defines the Flank Width Modulation, together with PBFM00 bit. Table 13-13.
PBFM01 0 0 1 1 1.
Flank Width Mode Selection
PBFM00 0 1 0 1 Description Flank Width Modulation operates on RB (On-Time 1 only). Flank Width Modulation operates on RB + RA (On-Time 0 and On-Time 1). Flank Width Modulation operates on SB (Dead-Time 1 only) (1). Flank Width Modulation operates on SB +SA (Dead-Time 0 and DeadTime 1).
Note: In one ramp mode, changing SA or SA+SB also affect On-Time ; see PSCr0 & PSCr1 Basic Waveforms in One Ramp mode
* Bit 4 - PAOC0B : PSCR Asynchronous Output Control B When this bit is set, Fault input selected to block B can act directly to PSCOUT01 output. See Section "PSCR Input Configuration", page 159. * Bit 3 - PAOC0A : PSCR Asynchronous Output Control A When this bit is set, Fault input selected to block A can act directly to PSCOUT00 output. See Section "PSCR Input Configuration", page 159. * Bit 2- PBFM00: Balance Flank Width Modulation, bit 0 Defines the Flank Width Modulation, together with PBFM01 bit * Bit 1 - PCCYC0 : PSCR Complete Cycle When this bit is set, the PSCR completes the entire waveform cycle before halt operation requested by clearing PRUN0. This bit is not relevant in slave mode (PARUN0 = 1). * Bit 0 - PRUN0 : PSCR Run Writing this bit to one starts the PSCR. When set, this bit prevails over PARUN0 bit.
13.23.8
PSCR Input A Control Register - PFRC0A
Bit Read/Write Initial Value 7 PCAE0A R/W 0 6 R/W 0 5 R/W 0 4 PFLTE0A R/W 0 3 PRFM0A3 R/W 0 2 PRFM0A2 R/W 0 1 PRFM0A1 R/W 0 0 PRFM0A0 R/W 0 PFRC0A
PISEL0A0 PELEV0A
13.23.9
PSCR Input B Control Register - PFRC0B
Bit Read/Write Initial Value 7 PCAE0B R/W 0 6 R/W 0 5 R/W 0 4 PFLTE0B R/W 0 3 PRFM0B3 R/W 0 2 PRFM0B2 R/W 0 1 PRFM0B1 R/W 0 0 PRFM0B0 R/W 0 PFRC0B
PISEL0B0 PELEV0B
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The Input Control Registers are used to configure the 2 PSC's Retrigger/Fault block A & B. The 2 blocks are identical, so they are configured on the same way. * Bit 7 - PCAE0x : PSCR Capture Enable Input Part x Writing this bit to one enables the capture function when external event occurs on input selected as input for Part x (see PISEL0x0 bit in the same register). * Bit 6 - PISEL0x0 : PSCR Input Select for Part x Together with PISEL0x1 in PSOC0 register, defines active signal on PSC module A. See Table 13-8 on page 171 and Table 13-9 on page 171 * Bit 5 -PELEV0x : PSCR Edge Level Selector of Input Part x When this bit is clear, the falling edge or low level of selected input generates the significative event for retrigger or fault function . When this bit is set, the rising edge or high level of selected input generates the significative event for retrigger or fault function. * Bit 4 - PFLTE0x : PSCR Filter Enable on Input Part x Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the retrigger pin is filtered. The filter function requires four successive equal valued samples of the retrigger pin for changing its output. The Input Capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. * Bit 3:0 - PRFM0x3:0: PSCR Fault Mode These four bits define the mode of operation of the Fault or Retrigger functions. (see PSCR Functional Specification for more explanations) Table 13-14.
PRFM0x3:0 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b
Level Sensitivity and Fault Mode Operation
Description
No action, PSCR Input is ignored
PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait
PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait PSCR Input Mode 3: Stop signal, Execute Opposite while Fault active PSCR Input Mode 4: Deactivate outputs without changing timing. PSCR Input Mode 5: Stop signal and Insert Dead-Time PSCR Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. PSCR Input Mode 7: Halt PSCR and Wait for Software Action PSCR Input Mode 8: Edge Retrigger PSC PSCR Input Mode 9: Fixed Frequency Edge Retrigger PSC
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Table 13-14.
PRFM0x3:0 1010b 1011b 1100b 1101b 1110b 1111b
Level Sensitivity and Fault Mode Operation
Description
Reserved (do not use)
PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate Output Reserved (do not use)
13.23.10
PSCR Input Capture Register - PICR0H and PICR0L
Bit 7 PCST0 Read/Write Initial Value R 0 6 - R 0 5 - R 0 4 - R 0 3 PICR0[11:8] PICR0[7:0] R 0 R 0 R 0 R 0 2 1 0 PICR0H PICR0L
* Bit 7 - PCST0 : PSCR Capture Software Trig bit Set this bit to trigger off a capture of the PSCR counter. When reading, if this bit is set it means that the capture operation was triggered by PCST0 setting otherwise it means that the capture operation was triggered by a PSCR input. The Input Capture is updated with the PSCR counter value each time an event occurs on the enabled PSCR input pin (or optionally on the Analog Comparator output) if the capture function is enabled (bit PCAE0x in PFRC0x register is set). The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit or 12-bit registers.
13.23.11
PSCR Interrupt Mask Register - PIM0
Bit Read/Write Initial Value 7 R 0 6 R 0 5 R 0 4 PEVE0B R/W 0 3 PEVE0A R/W 0 2 R 0 1 PEOEPE0 R 0 0 PEOPE0 R/W 0 PIM0
* Bit 7- 5 - Reserved * Bit 4 - PEVE0B : PSCR External Event B Interrupt Enable When this bit is set, an external event which can generates a capture from Retrigger/Fault block B generates also an interrupt. * Bit 3 - PEVE0A : PSCR External Event A Interrupt Enable When this bit is set, an external event which can generates a capture from Retrigger/Fault block A generates also an interrupt.
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* Bit 2 - Reserved * Bit 1- PEOEPE0 : PSCR End Of Enhanced Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSC reduced reaches the end of the 15th PSC cycle. This allows to update the PSCR values in the interrupt routine and to start a new enhanced cycle with the new values at the next PSCR cycle end. * Bit 0 - PEOPE0 : PSCR End Of Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSCR reaches the end of the whole cycle. 13.23.12 PSCR Interrupt Flag Register - PIFR0
Bit Read/Write Initial Value 7 POAC0B R 0 6 POAC0A R 0 5 R 0 4 PEV0B R/W 0 3 PEV0A R/W 0 2 PRN01 R 0 1 PRN00 R 0 0 PEOP0 R/W 0 PIFR0
* Bit 7 - POAC0B : PSCR Output B Activity This bit is set by hardware each time the output PSCOUT01 changes from 0 to 1 or from 1 to 0. Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSCR output doesn't change due to a frozen external input signal. * Bit 6 - POAC0A : PSCR Output A Activity This bit is set by hardware each time the output PSCOUT00 changes from 0 to 1 or from 1 to 0. Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSCR output doesn't change due to a freezen external input signal. * Bit 5 - Reserved * Bit 4 - PEV0B : PSCR External Event B Interrupt This bit is set by hardware when an external event which can generates a capture or a retrigger from Retrigger/Fault block B occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVE0B bit = 0). * Bit 3 - PEV0A : PSCR External Event A Interrupt This bit is set by hardware when an external event which can generates a capture or a retrigger from Retrigger/Fault block A occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVE0A bit = 0). * Bit 2:1 - PRN01:0 : PSCR Ramp Number Memorization of the ramp number when the last PEV0A or PEV0B occurred.
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Table 13-15.
PRN01 0 0 1 1
PSCR Ramp Number Description
PRN00 0 1 0 1 Description The last event which has generated an interrupt occurred during ramp 1 The last event which has generated an interrupt occurred during ramp 2 The last event which has generated an interrupt occurred during ramp 3 The last event which has generated an interrupt occurred during ramp 4
* Bit 0 - PEOP0: End Of PSCR Interrupt This bit is set by hardware when PSCR achieves its whole cycle. Must be cleared by software by writing a one to its location.
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14. Serial Peripheral Interface - SPI:
14.1 Features
* * * * * * * *
Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode
14.2
Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90PWM81 and peripheral devices or between several AVR devices. The AT90PWM81 SPI includes the following features Figure 14-1. SPI Block Diagram(1)
MISO
clk IO
MOSI
DIVIDER /2/4/8/16/32/64/128
SCK
SPI2X
SS
Note:
1. Refer to Figure 2-1 on page 3, and Table 9-3 on page 73 for SPI pin placement.
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The interconnection between Master and Slave CPUs with SPI is shown in Figure 14-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out - Slave In, MOSI, line, and from Slave to Master on the Master In - Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of transmission flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 14-2. SPI Master-slave Interconnection
SHIFT ENABLE
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed fclkio/4.
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 14-1. For more details on automatic port overrides, refer to "Alternate Port Functions" on page 71. Table 14-1.
Pin MOSI MISO SCK SS
SPI Pin Overrides(1)
Direction, Master SPI User Defined Input User Defined User Defined Direction, Slave SPI Input User Defined Input Input
Note:
1. See "Alternate Functions of Port B" on page 73 for a detailed description of how to define the direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB.
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Assembly Code Example(1)
SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi out ldi out ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete sbis SPSR,SPIF rjmp Wait_Transmit ret r17,(1<; Enable SPI, Master, set clock rate fck/16
C Code Example(1)
void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
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Assembly Code Example(1)
SPI_SlaveInit: ; Set MISO output, all others input ldi out ldi out ret SPI_SlaveReceive: ; Wait for reception complete sbis SPSR,SPIF rjmp SPI_SlaveReceive ; Read received data and return in ret r16,SPDR r17,(1<; Enable SPI
C Code Example(1)
void SPI_SlaveInit(void) { /* Set MISO output, all others input */ DDR_SPI = (1<14.3
14.3.1
SS Pin Functionality
Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
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The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 14.3.2 Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be driving the SS pin of the SPI Slave. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. 2. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave, the MOSI and SCK pins become inputs. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode.
14.4
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 14-3 and Figure 14-4. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 14-3 and Table 14-4, as done below: Table 14-2. CPOL Functionality
Leading Edge CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) Trailing eDge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) SPI Mode 0 1 2 3
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Figure 14-3.
SPI Transfer Format with CPHA = 0
SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
Figure 14-4.
SPI Transfer Format with CPHA = 1
SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) LSB first (DORD = 1)
MSB LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
14.5
14.5.1
SPI registers
SPI Control Register - SPCR
Bit Read/Write Initial Value 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR
* Bit 7 - SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set. * Bit 6 - SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
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* Bit 5 - DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. * Bit 4 - MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. * Bit 3 - CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 14-3 and Figure 14-4 for an example. The CPOL functionality is summarized below: Table 14-3. CPOL Functionality
CPOL 0 1 Leading Edge Rising Falling Trailing Edge Falling Rising
* Bit 2 - CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 14-3 and Figure 14-4 for an example. The CPOL functionality is summarized below: Table 14-4. CPHA Functionality
CPHA 0 1 Leading Edge Sample Setup Trailing Edge Setup Sample
* Bits 1, 0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clkIO frequency fclkio is shown in the following table: Table 14-5.
SPI2X 0 0 0 0 1 1 1 1
Relationship Between SCK and the Oscillator Frequency
SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK Frequency
fclkio/4 fclkio/16 fclkio/64 fclkio/128 fclkio/2 fclkio/8 fclkio/32 fclkio/64
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14.5.2
SPI Status Register - SPSR
Bit Read/Write Initial Value 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 SPI2X R/W 0 SPSR
* Bit 7 - SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR). * Bit 6 - WCOL: Write COLlision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. * Bit 5..1 - Res: Reserved Bits These bits are reserved bits in the AT90PWM81 and will always read as zero. * Bit 0 - SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 14-5). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fclkio/4 or lower. The SPI interface on the AT90PWM81 is also used for program memory and EEPROM downloading or uploading. See Serial Programming Algorithm261 for serial programming and verification. 14.5.3 SPI Data Register - SPDR
Bit Read/Write Initial Value 7 SPD7 R/W X 6 SPD6 R/W X 5 SPD5 R/W X 4 SPD4 R/W X 3 SPD3 R/W X 2 SPD2 R/W X 1 SPD1 R/W X 0 SPD0 R/W X Undefined SPDR
* Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
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15. Voltage Reference and Temperature Sensor
15.1 Features
* Accurate Voltage Reference of 2.56V * Internal Temperature Sensor * Possibility for Runtime Compensation of Temperature Drift in Both Voltage Reference and On Chip
Oscillators * Low Power Consumption
15.2
On Chip voltage Reference and Temperature sensor overview
A low power band-gap reference provides AT90PWM81 with an accurate On-chip Bandgap voltage of 1.100 V (Vbg). Then when SW1 is off and SW2/SW3 is on, the bandgap voltage is multiplied and generates the internal reference VREF of 2.56V. This reference voltage is used as reference for the ADC, the DAC and can use a buffer with external decoupling capacitor (when SW0 is on) to enable excellent noise performance with minimum power consumption as shown on Figure 15-1. The selection of the Voltage Reference for all the analog components (ADC, DAC, Comparators) is done using the REFS1:0 bits in ADMUX register; see "ADC Multiplexer Register - ADMUX" on page 216. For conditions using the Bandgap and the internal voltage reference, see "Bandgap and Internal Voltage Reference Enable Signals and Start-up Time" on page 54
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Figure 15-1.
Reference Circuitry
Aref SW0 REFS0,REFS1 are used to control SW0..3 SW1 Vref Voltage Ref rence e
AVc c
VPTAT Vbg BG Ref erence
BG Calibr ation Fus es BG Calibr ation Reg isters BGCC BGCRR R,
SW2 /1.60 /2.13 /3.20 ADC /6.40
Comp SW3
AT90PWM81 has an On-chip temperature sensor for monitoring the die temperature. A voltage Proportional-To-Absolute-Temperature, VPTAT, is generated in the voltage reference circuit and after buffering, is connected to the ADC multiplexer. This temperature sensor can be used for runtime compensation of temperature drift in both the voltage reference and the On-chip Oscillator. To get the absolute temperature in degrees Kelvin, the measured Vtemp voltage must be scaled with the Vtemp factory calibration value stored in the signature row. See Section "Temperature Measurement", page 192 for details. Vbg and Vtemp can be measured with the integrated ADC by selecting the proper ADC channel with ADMUX (see See "ADC Multiplexer Register - ADMUX" on page 216.).
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15.3
15.3.1
Register Description
BGCCR - Bandgap Calibration Current Register
Bit Read/Write Initial Value
7 0
6 0
5 0
4 0
3 BGCC3 R/W 1
2 BGCC2 R/W 0
1 BGCC1 R/W 0
0 BGCC0 R/W 0 BGCCR
* Bit 7:4 - Res: Reserved Bit This bit is reserved for future use. * Bit 3:0 - BGCC3:0: BG Calibration of PTAT Current These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary coded, so the lowest value for Vbg is reached when BGCC3:0 is 0000 and the maximum value when BGCC3:0 is 1111. The step size is approximately 5 mV. Updating the BGCC bits will affect the BOD detection level. The BOD will react quickly to the new detection level. 15.3.2 BGCRR - Bandgap Calibration Resistor Register
Bit Read/Write Initial Value 7 0 6 0 5 0 4 0 3 BGCR3 R/W 1 2 BGCR2 R/W 0 1 BGCR1 R/W 0 0 BGCR0 R/W 0 BGCRR
* Bit 7:4 - Res: Reserved Bit This bit is reserved for future use. * Bit 3:0 - BGCR3:0: BG Calibration of Resistor ladder These bits are used for temperature gradient adjustment of the bandgap reference. Figure 15-2 illustrates Vbg as a function of temperature. Vbg has a positive temperature coefficient at low temperatures and negative temperature coefficient at high temperatures. Depending on the process variations, the top of the Vbg curve may be located at higher or lower temperatures. To minimize the temperature drift in the temperature range of interest, BGCRR is used to adjust the top of the curve towards the centre of the temperature range of interest. The BGCRR bits are thermometer coded, resulting in 5 possible settings: 0000, 0001, 0011, 0111, 1111. The value 0000 shifts the top of the Vbg curve to the highest possible temperature, and the value 1111 shifts the top of the Vbg curve to the lowest possible temperature.
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Figure 15-2.
1.5
Illustration of Vbg as a function of temperature.
BGCRR is used to move the top of the Vbg curve to the center of the temperature range of interest 1.0 Temperature range of interest
0.5
-40
-20
-0
20
40
60
80
100
Temperature (C)
15.4
Temperature Measurement
The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended ADC12 channel, as shown on Figure 15-3.
Figure 15-3.
Temperature sensor Circuitry
Enable when ADEN=1 VPTAT Current-voltage Convertor
Enable when ADC Mux=1100 + Vtemp
BG Ref erence
ADC Mux=1100
Selecting the ADC12 channel by writing the MUX3..0 bits in ADMUX register to "1100" enables the temperature sensor (see See "ADC Multiplexer Register - ADMUX" on page 216.). The recommended ADC voltage reference source is the internal 2.56V voltage reference for temperature sensor measurement. When the temperature sensor is enabled, the ADC converter can be used in single conversion mode to measure the voltage over the temperature sensor. The amplifier allows to charge the ADC sample capacitor at full CKadc clock speed. The measured voltage has a linear relationship to temperature as 192
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described in Table 15-1. When the voltage reference equals 2.56V, the conversion result has approximately a 1 LSB/C (or 2.5 mV/C) correlation to temperature and the typical accuracy of the temperature measurement is +/- 10C after offset calibration. Table 15-1.
Temperature Voltage (mV) ADC
Temperature vs. Sensor Output Voltage (Typical Case)
-40C 600 240 25C 762 305 105C 125C 1012 405
The values described in Table 15-1 are typical values. However, due to the process variation the temperature sensor output voltage varies from one chip to another. To be capable of achieving more accurate results the temperature measurement can be calibrated in the application software. When using temperature sensor, the temperature (in Kelvin) is calculated as follows: T = A * Tptat + B, where A Gain correction multiplier (constant '1', or unsigned fixed point number) B Offset correction term (2. complement signed byte) Tptat ADC result when measuring temperature sensor voltage, Vref with 2.56V internal reference T Temperature in Kelvin ('K = 'C + 273) Example: If A=0x80 (=1.00) and B=8, and ADC result is 0x15E (=350), this gives a measured temperature of: T = 1.00 * 350 + 8 = 358 K (+85C) 15.4.1 Manufacturing Calibration One can also use the calibration values available in the signature row See "Reading the Signature Row from Software" on page 243. The calibration values are determined from values measured during test at room temperature which is approximatively +25C. Calibration measures are done at Vcc = 3V and with ADC in internal Vref (1.1V) mode. The temperature in Celsius degrees can be calculated utilizing the formula: T = ((([ (ADCH << 8) | ADCL ] -(273 + 25-TSOFFSET)) * TSGAIN)/128) + 25 Where: a. ADCH & ADCL are the ADC data registers, b. TSGAIN is the temperature sensor gain (unsigned fixed point 8-bit temperature sensor gain factor in 1/128th units stored as previously in the signature row at address 0x0007) See "Reading the Signature Row from Software" on page 243. c. TSOFFSET is the temperature sensor offset correction term (signed twos complement 7-bit temperature sensor offset reading stored as previously in the signature row at address 0x0005)
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16. Analog Comparator
The Analog Comparator compares the input values on the positive pin ACMPx and negative pin ACMPM or ACMPMx.
16.1
Features
* * * * *
3 Analog Comparators High Speed analog Comparators +/-25mV or +/-10mV or 0 Hysteresis 4 reference levels Generation of Configurable Interrupts
16.2
Overview
The AT90PWM81 features 3 fast analog comparators. Each comparator has a dedicated input on the positive input, and the negative input of each comparator can be configured as: * a steady value among the 4 internal reference levels defined by the Vref selected thanks to the REFS1:0 bits in ADMUX register. * a value generated from the internal DAC * an external analog input ACMPMx. When the voltage on the positive ACMPn pin is higher than the voltage selected by the ACnM multiplexer on the negative input, the Analog Comparator output, ACnO, is set. Each comparator can trigger a separate interrupt, exclusive to the Analog Comparator. In addition, the user can select Interrupt triggering on comparator output rise, fall or toggle. The interrupt flags can also be used to synchronize ADC or DAC conversions. Moreover, the comparator's output of the comparator 1 can be set to trigger the Timer/Counter1 Input Capture function. A block diagram of the comparators and their surrounding logic is shown in Figure 16-1.
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Figure 16-1.
AC1 OE ACMP1_OUT AC1 H 210 ACMP1 Band Gap AC1 IE AC1 EN ACMPM1 AC1 ICE AC2 OE AC2 OI AC1 M 210 AC1 IS1 AC1 IS0 T1 Captur T e rigger + Interrupt Sensitivity Con trol Analog Compar tor 1 Interrupt a AC1 (to PSCR) O
Analog Comparator Block Diagram
AC1 OI
AC1 IF
ACMP2_OUT
AC2 (to PSC2) O AC2 IF AC2 H 210 Interrupt Sensitivity Con trol Analog Compar tor 2 Interrupt a
ACMP2 Band Gap
+ AC2 IS1 ACMPM2 AC3 OEA AC2 EN ACMP3_OUT_A AC3 OE ACMP3_OUT ACMP3 Band Gap AC3 OI AC2 M 210 AC2 IS0
AC2 IE
AC3 (to PSC2) O AC3 IF AC3 H 210 + Interrupt Sensitivity Con trol Analog Compar tor 3 Interrupt a
AC3 IE AC3 IS1 AC3 IS0
ACMPM3 ACMPM DAC Res ult AC3 M 210
-
AC3 EN
Vref
DAC10
DAC EN Aref REFS0 AVcc Internal 2.56V Ref rence e Vref /1.60 /2.13 /3.20 /6.40
REFS1
REFS0 +REFS1
Notes:
1. .Refer to Figure 2-1 on page 3 and for Analog Comparator pin placement 2. The voltage on Vref is defined in 17-3 "ADC Voltage Reference Selection" on page 217
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Figure 16-2.
Comparator PSC links
+ -
ACM P1 ACM PM1
AC1 EN
PSCINr PSCINrA PSCINrB PSCR PSCIN 2
ACM P2 ACM PM2
+ AC2 EN
PSCIN2A ACM P3 ACM PM3 + -
PSC2
AC3 EN
16.3
Shared pins between Analog Comparator and ADC
Several Analog comparators input pins can also be used as ADC inputs, so it is possible to measure the comparison voltages. However, when a comparator input is selected as the ADC input, a spike occurs during the sampling phase of the ADC. This may lead to an unwanted transition on the comparator output. So it is a safe software practice to devalidate the comparator output before measuring the voltage on one of the inputs.
16.4
Analog Comparator Register Description
Each analog comparator has its own control register. A dedicated register has been designed to consign the outputs and the flags of the 3 analog comparators.
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16.4.1 Analog Comparator 1Control Register - AC1CON
Bit Read/Write Initial Value 7 AC1EN R/W 0 6 AC1IE R/W 0 5 AC1IS1 R/W 0 4 AC1IS0 R 0 3 R/W 0 2 AC1M2 R/W 0 1 AC1M1 R/W 0 0 AC1M0 R/W 0 AC1CON
* Bit 7- AC1EN: Analog Comparator 1 Enable Bit Set this bit to enable the analog comparator 1. Clear this bit to disable the analog comparator 1. * Bit 6- AC1IE: Analog Comparator 1 Interrupt Enable bit Set this bit to enable the analog comparator 1 interrupt. Clear this bit to disable the analog comparator 1 interrupt. * Bit 5, 4- AC1IS1, AC1IS0: Analog Comparator 1 Interrupt Select bit These 2 bits determine the sensitivity of the interrupt trigger. The different setting are shown in Table 16-1. Table 16-1.
AC1IS1 0 0 1 1
Interrupt sensitivity selection
AC1IS0 0 1 0 1 Description Comparator Interrupt on output toggle Reserved Comparator interrupt on output falling edge Comparator interrupt on output rising edge
* Bit 3- Reserved
* Bit 2, 1, 0- AC1M2, AC1M1, AC1M0: Analog Comparator 1 Multiplexer register These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 16-2. Table 16-2.
AC1M2 0 0 0 0 1 1 1 1
Analog Comparator 1 negative input selection
AC1M1 0 0 1 1 0 0 1 1 AC1M0 0 1 0 1 0 1 0 1 Description "Vref"/6.40 "Vref"/3.20 "Vref"/2.13 "Vref"/1.60 Band Gap voltage DAC result Analog Comparator Negative Input (ACMPM1 pin) Analog Comparator Negative Input (ACMPM pin)
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16.4.2
Analog Comparator 2 Control Register - AC2CON
Bit Read/Write Initial Value 7 AC2EN R/W 0 6 AC2IE R/W 0 5 AC2IS1 R/W 0 4 AC2IS0 R/W 0 3 -R 0 2 AC2M2 R/W 0 1 AC2M1 R/W 0 0 AC2M0 R/W 0 AC2CON
* Bit 7- AC2EN: Analog Comparator 2 Enable Bit Set this bit to enable the analog comparator 2. Clear this bit to disable the analog comparator 2. * Bit 6- AC2IE: Analog Comparator 2 Interrupt Enable bit Set this bit to enable the analog comparator 2 interrupt. Clear this bit to disable the analog comparator 2 interrupt. * Bit 5, 4- AC2IS1, AC2IS0: Analog Comparator 2 Interrupt Select bit These 2 bits determine the sensitivity of the interrupt trigger. The different setting are shown in Table 16-3. Table 16-3.
AC2IS1 0 0 1 1
Interrupt sensitivity selection
AC2IS0 0 1 0 1 Description Comparator Interrupt on output toggle Reserved Comparator interrupt on output falling edge Comparator interrupt on output rising edge
* Bit 3- Reserved * Bit 2, 1, 0- AC2M2, AC2M1, AC2M0: Analog Comparator 2 Multiplexer register These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 16-4. Table 16-4.
AC2M2 0 0 0 0 1 1 1 1
Analog Comparator 2 negative input selection
AC2M1 0 0 1 1 0 0 1 1 AC2M0 0 1 0 1 0 1 0 1 Description "Vref"/6.40 "Vref"/3.20 "Vref"/2.13 "Vref"/1.60 Band Gap voltage DAC result Analog Comparator Negative Input (ACMPM2 pin) Analog Comparator Negative Input (ACMPM pin)
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16.4.3 Analog Comparator 3 Control Register - AC3CON
Bit Read/Write Initial Value 7 AC3EN R/W 0 6 AC3IE R/W 0 5 AC3IS1 R/W 0 4 AC3IS0 R/W 0 3 AC3OEA 0 2 AC3M2 R/W 0 1 AC3M1 R/W 0 0 AC3M0 R/W 0 AC3CON
* Bit 7- AC3EN: Analog Comparator 3 Enable Bit Set this bit to enable the analog comparator 3. Clear this bit to disable the analog comparator 3. * Bit 6- AC3IE: Analog Comparator 3 Interrupt Enable bit Set this bit to enable the analog comparator 3 interrupt. Clear this bit to disable the analog comparator 3 interrupt. * Bit 5, 4- AC3IS1, AC3IS0: Analog Comparator 3 Interrupt Select bit These 2 bits determine the sensitivity of the interrupt trigger. The different setting are shown in Table 16-5. Table 16-5.
AC3IS1 0 0 1 1
Interrupt sensitivity selection
AC3IS0 0 1 0 1 Description Comparator Interrupt on output toggle Reserved Comparator interrupt on output falling edge Comparator interrupt on output rising edge
* Bit 3- AC3OEA: Analog Comparator 3 Alternate Output Enable Set this bit to enable the analog comparator 3 alternate output pin. Clear this bit to disable the analog comparator 3 alternate output pin.
* Bit 2, 1, 0- AC3M2, AC3M1, AC3M0: Analog Comparator 3 Multiplexer register These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 16-4. Table 16-6.
AC3M2 0 0 0 0 1 1 1 1
Analog Comparator 2 negative input selection
AC3M1 0 0 1 1 0 0 1 1 AC3M0 0 1 0 1 0 1 0 1 Description "Vref"/6.40 "Vref"/3.20 "Vref"/2.13 "Vref"/1.60 Band Gap voltage DAC result Analog Comparator Negative Input (ACMPM3 pin) Analog Comparator Negative Input (ACMPM pin)
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16.4.4
Analog Comparator n Extended Control Register - ACnECON
Bit Read/Write Initial Value 0 0 7 6 5 ACnOI R/W 0 4 ACnOE R/W 0 3 AC1ICE R/W 0 2 ACnH2 R/W 0 1 ACnH1 R/W 0 0 ACnH0 R/W 0 ACnECON
* Bit 7..6- Reserved * Bit 5- AC1OI: Analog Comparator n Output Invert Set this bit to invert the analog comparator n output . Clear this bit to keep the analog comparator n output . * Bit 4- AC1OE: Analog Comparator n Output Enable Set this bit to enable the analog comparator n output pin. Clear this bit to disable the analog comparator n output pin. * Bit 3 - AC1ICE: Analog Comparator 1 Interrupt Capture Enable bit Set this bit to enable the input capture of the Timer/Counter1 on the analog comparator event. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. In case ICES1 bit ("Timer/Counter1 Control Register B - TCCR1B" on page 96) is set high, the rising edge of AC3O is the capture/trigger event of the Timer/Counter1, in case ICES1 is set to zero, it is the falling edge which is taken into account. Clear this bit to disable this function. In this case, no connection between the Analog Comparator and the input capture function exists
* Bit 2, 1, 0- ACnH2, ACnH1, ACnH0: Analog Comparator n Hysteresis select These 3 bits determine the hysteresis value of the analog comparator The different setting are shown in Table 16-7. Table 16-7.
AC1M2 0 0 0 0 1 1 1 1
Analog Comparator n Hysteresis selection
AC1M1 0 0 1 1 0 0 1 1 AC1M0 0 1 0 1 0 1 0 1 Description No Hysteresis Hysteresis + 10 mV Hysteresis - 10 mV Hysteresis +- 10 mV Reserved Hysteresis + 25 mV Hysteresis - 25 mV Hysteresis +- 25 mV
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16.4.5 Analog Comparator Status Register - ACSR
Bit Read/Write Initial Value 7 AC3IF R/W 0 6 AC2IF R/W 0 5 AC1IF R/W 0 4 R/W 0 3 AC3O 0 2 AC2O R 0 1 AC1O R 0 0 R 0 ACSR
* Bit 7- AC3IF: Analog Comparator 3 Interrupt Flag Bit This bit is set by hardware when comparator 3 output event triggers off the interrupt mode defined by AC3IS1 and AC3IS0 bits in AC3CON register. This bit is cleared by hardware when the corresponding interrupt vector is executed in case the AC3IE in AC3CON register is set. Anyway, this bit is cleared by writing a logical one on it. This bit can also be used to synchronize ADC or DAC conversions.. * Bit 6- AC2IF: Analog Comparator 2 Interrupt Flag Bit This bit is set by hardware when comparator 2 output event triggers off the interrupt mode defined by AC2IS1 and AC2IS0 bits in AC2CON register. This bit is cleared by hardware when the corresponding interrupt vector is executed in case the AC2IE in AC2CON register is set. Anyway, this bit is cleared by writing a logical one on it. This bit can also be used to synchronize ADC or DAC conversions. * Bit 5- AC1IF: Analog Comparator 1 Interrupt Flag Bit This bit is set by hardware when comparator 1 output event triggers off the interrupt mode defined by AC1IS1 and AC1IS0 bits in AC1CON register. This bit is cleared by hardware when the corresponding interrupt vector is executed in case the AC1IE in AC1CON register is set. Anyway, this bit is cleared by writing a logical one on it. This bit can also be used to synchronize ADC or DAC conversions. * Bit 4- Reserved * Bit 3- AC3O: Analog Comparator 3 Output Bit AC2O bit is directly the output of the Analog comparator 2. Set when the output of the comparator is high. Cleared when the output comparator is low. * Bit 2- AC2O: Analog Comparator 2 Output Bit AC2O bit is directly the output of the Analog comparator 2. Set when the output of the comparator is high. Cleared when the output comparator is low. * Bit 1- AC1O: Analog Comparator 1 Output Bit AC1O bit is directly the output of the Analog comparator 1. Set when the output of the comparator is high. Cleared when the output comparator is low. Bit 0- Reserved
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16.4.6
Digital Input Disable Register 0 - DIDR0
Bit 7 ADC8D AMP3D Read/Write Initial Value R/W 0 6 ADC7D AMP0-D R/W 0 5 ADC5D ACMP2D R/W 0 4 3 2 1 0 ADC0D ACMP1D R/W 0 DIDR0
ADC4D ADC3D ACMP3MD ACMPMD R/W 0 R/W 0
ADC2D ADC1D ACMP2MD R/W 0 R/W 0
* Bit 7:0 - ACMPMxD and ACMPxD: ACMPxMD, ACMPxD & APM0+Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding Analog pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to one of these pins and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 16.4.7 Digital Input Disable Register 1- DIDR1
Bit Read/Write Initial Value 7 0 6 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 ADC10D R/W 0 0 ADC9D R/W 0 DIDR1
ACMP1MD AMP0+D
* Bit 3, 0: ACMPxMD, ACMPxD & APM0+ Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding analog pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to one of these pins and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
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17. Analog to Digital Converter - ADC
17.1 Features
* * * * * * * * * * * * * * *
10-bit Resolution 0.5 LSB Integral Non-linearity 2 LSB Absolute Accuracy 8- 250 s Conversion Time Up to 120 kSPS at Maximum Resolution 11 Multiplexed Single Ended Input Channels One Differential input channels with accurate (5%) programmable gain 5, 10, 20 and 40 Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.56 V ADC Reference Voltage Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler Temperature sensor
The AT90PWM81 features a 10-bit successive approximation ADC. The ADC is connected to an 15channel Analog Multiplexer which allows eleven single-ended input. The single-ended voltage inputs refer to 0V (GND). The device also supports 2 differential voltage input combinations which are equipped with a programmable gain stage, providing amplification steps of 14dB (5x), 20 dB (10x), 26 dB (20x), or 32dB (40x) on the differential input voltage before the A/D conversion. On the amplified channels, 8-bit resolution can be expected. The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 17-1. The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than 0.3V from VCC. See the paragraph "ADC Noise Canceler" on page 209 on how to connect this pin. Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance.
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Figure 17-1.
Analog to Digital Converter Block Schematic
AREF/ADC6 AVCC Internal 2.56V Reference Vref Logic ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC8 ADC9 ADC10 AMP0-/ADC7 AMP0+ Temp Sensor VCC/4 GND Bandgap REFS0,REFS1
Coarse/Fine DAC
10
+ AMP0GS +
10
ADCH ADCL
SAR
10
CKADC CKADC
CONTR OL
ADC CONVERSION COMPLETE IRQ
AMP0CSR
CK
PRESCALER
REFS1
REFS0
ADLAR
MUX3
ADMUX
MUX2
MUX1
MUX0
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
ADCSRA
Sources
Edge Detector
ADATE
3
ADHSM ADNCDIS
-
ADSSEN ADTS3
ADCSRB
ADTS2
ADTS1
ADTS0
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17.2 Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel are selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference is set by the REFS1 and REFS0 bits in ADMUX register, whatever the ADC is enabled or not. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completed before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. The ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
17.3
Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal is still set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. Triggering from the PSC's synchronization signal is different as there is no flag. In this case, a new conversion is started at each triggering signal. However, a single shot mode can be activated by setting the bit ADSSEN in ADCSRB register. In this case the synchronization signal is blocked until the ADCH registed is read.
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Figure 17-2.
ADC Auto Trigger Logic
ADTS[2:0] PRESCALER
START ADIF SOURCE 1 . . . . SOURCE n ADSC ADATE
CLKADC
CONVERSION LOGIC EDGE DETECTOR
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. The free running mode is not allowed on the amplified channels. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started.
17.4
Prescaling and Conversion Timing
Figure 17-3. ADC Prescaler
ADEN START CK
CK/128 CK/16 CK/32 CK/64 CK/2 CK/4 CK/8
Reset 7-BIT ADC PRESCALER
ADPS0 ADPS1 ADPS2
ADC CLOCK SOURCE
By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 2 MHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 2 MHz to get a higher sample rate. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
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When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See "Changing Channel or Reference Selection" on page 208 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 3.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place (four XXX to be confirmed) two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 17-1. Figure 17-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
First Conversion Next Conversion
Cycle Number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock ADEN ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result MUX and REFS Update
MUX and REFS Update
Sample & Hold
Conversion Complete
Figure 17-5.
ADC Timing Diagram, Single Conversion
One Conversion Next Conversion
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete
MUX and REFS Update
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Figure 17-6.
ADC Timing Diagram, Auto Triggered Conversion
One Conversion Next Conversion
Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL
1
2
3
4
5
6
7
8
13
14
15
16
1
2
Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete Prescaler Reset
Prescaler Reset
Figure 17-7.
ADC Timing Diagram, Free Running Conversion
One Conversion 14 15 16 Next Conversion 1 2 3 4
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
Sign and MSB of Result LSB of Result
Conversion Complete
Sample & Hold MUX and REFS Update
Table 17-1.
ADC Conversion Time
Normal Conversion, Single Ended 3.5 15.5 Auto Triggered Conversion 4 16
Condition Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles)
First Conversion 13.5 25
17.5
Changing Channel or Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written.
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If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: a. b. c. When ADATE or ADEN is cleared. During conversion, minimum one ADC clock cycle after the trigger event. After a conversion, before the interrupt flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. 17.5.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: * In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. * In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. * In Free Running mode, because the amplifier clear the ADSC bit at the end of an amplified conversion, it is not possible to use the free running mode, unless ADSC bit is set again by soft at the end of each conversion. 17.5.2 ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. If the external AREF pin is connected to the ADC, the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant voltmeter. Note that VREF is a high impedant source, and only a capacitive load should be connected in a system. The user may switch between AVCC, AREF pin and 2.56V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 24-5 on page 281.
17.6
ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used:
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a. b. c.
Make sure the ADNCDIS bit is reset Make sure the ADATE bit is reset Make sure that the ADC is enabled and is not busy converting (ADSC reset). Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed.
d. e.
Another possible procedure is possible for Auto trigger conversions: a. b. c. d. Make sure the ADNCDIS bit is set Make sure the ADATE bit is set Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion on the next triggering event. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. If the ADC is enabled in such sleep modes and the user wants to perform differential conversions, the user is advised to switch the ADC off and on after waking up from sleep to prompt an extended conversion to get a valid result. 17.6.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 17-8 An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 5 k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, witch can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. If differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a few hundred k or less is recommended. Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. 210
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Figure 17-8. Analog Input Circuitry
IIH ADCn 1..100 k CS/H= 14 pF IIL VCC/2
17.6.2
Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. b. c. d. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as shown in Figure 17-9. Use the ADC noise canceler function to reduce induced noise from the CPU. If any ADC port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. ADC Power Connections
Figure 17-9.
10 H
VCC GND
AREF AGND AVCC
100nF Analog Ground Plane
17.6.3 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by shortening both
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differential inputs using the AMPxIS bit with both inputs unconnected. (See "Amplifier 0 Control and Status register - AMP0CSR" on page 224.). This offset residue can be then subtracted in software from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced below one LSB. 17.6.4 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: * Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 17-10. Offset Error
Output Code
Ideal ADC Actual ADC
Offset Error
VREF Input Voltage
* Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB
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Figure 17-11. Gain Error
Output Code Gain Error
Ideal ADC Actual ADC
VREF Input Voltage
* Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 17-12. Integral Non-linearity (INL)
Output Code
* Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
INL
Ideal ADC Actual ADC
VREF
Input Voltage
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Figure 17-13. Differential Non-linearity (DNL)
Output Code 0x3FF
1 LSB
DNL
0x000 0 VREF Input Voltage
* Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB. * Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, nonlinearity, and quantization error. Ideal value: 0.5 LSB.
17.7
ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is:
V IN 1023 ADC = -----------------------V REF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 17-3 on page 217 and Table 17-4 on page 217). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage. If differential channels are used, the result is: ( V POS - V NEG ) GAIN 512 ADC = ---------------------------------------------------------------------V REF where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, GAIN the selected gain factor and VREF the selected voltage reference. The result is presented in two's complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user wants to perform a quick polarity check of the result, it is sufficient to read the MSB of the result (ADC9 in ADCH). If the bit is one, the
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result is negative, and if this bit is zero, the result is positive. Figure 17-14 shows the decoding of the differential input range. Table 82 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is selected with a reference voltage of VREF. Figure 17-14. Differential Measurement Range
Output Code 0x1FF
0x000 - VREF /Gain 0x3FF 0 VREF/Gain Differential Input Voltage (Volts)
0x200
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Table 17-2.
VADCn
Correlation Between Input Voltage and Output Codes
Read code 0x1FF 0x1FF 0x1FE ... 0x001 0x000 0x3FF ... 0x201 0x200 Corresponding decimal value 511 511 510 ... 1 0 -1 ... -511 -512
VADCm + VREF /GAIN VADCm + 0.999 VREF /GAIN VADCm + 0.998 VREF /GAIN ... VADCm + 0.001 VREF /GAIN VADCm VADCm - 0.001 VREF /GAIN ... VADCm - 0.999 VREF /GAIN VADCm - VREF /GAIN
Example 1: - ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) - Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. - ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 - ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. Example 2: - ADMUX = 0xFB (ADC3 - ADC2, 1x gain, 2.56V reference, left adjusted result) - Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. - ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029. - ADCL will thus read 0x40, and ADCH will read 0x0A. Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29.
17.8
ADC Register Description
The ADC of the AT90PWM81 is controlled through 3 different registers. The ADCSRA and The ADCSRB registers which are the ADC Control and Status registers, and the ADMUX which allows to select the Vref source and the channel to be converted. The conversion result is stored on ADCH and ADCL register which contain respectively the most significant bits and the less significant bits.
17.8.1
ADC Multiplexer Register - ADMUX
Bit Read/Write Initial Value 7 REFS1 R/W 0 6 REFS0 R/W 0 5 ADLAR R/W 0 4 -R 0 3 MUX3 R/W 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX
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* Bit 7, 6 - REFS1, 0: ADC Vref Selection Bits These 2 bits determine the voltage reference for the ADC and for the other analog devices. The different setting are shown in Table 17-3. Table 17-3.
REFS1
ADC Voltage Reference Selection
REFS0 Description Voltage Reference PE3/AREF pin External Voltage reference
0 0 1 1
0 1 0 1
External Vref AVcc Internal 2.56V Reference voltage Internal 2.56V Reference voltage
External capacitor for decoupling of the Internal Reference voltage PE3 pin free as port
If these bits are changed during a conversion, the change will not take effect until this conversion is complete (it means while the ADIF bit in ADCSRA register is set). In case the internal Vref is selected, it is turned ON as soon as an analog feature needed it is set. * Bit 5 - ADLAR: ADC Left Adjust Result Set this bit to left adjust the ADC result. Clear it to right adjust the ADC result. The ADLAR bit affects the configuration of the ADC result data registers. Changing this bit affects the ADC data registers immediately regardless of any on going conversion. For a complete description of this bit, see Section "ADC Result Data Registers - ADCH and ADCL", page 220. * Bit 3, 2, 1, 0 - MUX3, MUX2, MUX1, MUX0: ADC Channel Selection Bits These 4 bits determine which analog inputs are connected to the ADC input. The different setting are shown in Table 17-4. Table 17-4.
MUX3 0 0 0 0 0 0 0 0 1 1 1 1 1
ADC Input Channel Selection
MUX2 0 0 0 0 1 1 1 1 0 0 0 0 1 MUX1 0 0 1 1 0 0 1 1 0 0 1 1 0 MUX0 0 1 0 1 0 1 0 1 0 1 0 1 0 Description ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 AMP0 Temp sensor (Vtemp)
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Table 17-4.
MUX3 1 1 1
ADC Input Channel Selection
MUX2 1 1 1 MUX1 0 1 1 MUX0 1 0 1 Description VCC/4 Bandgap (Vbg) GND
If these bits are changed during a conversion, the change will not take effect until this conversion is complete (it means while the ADIF bit in ADCSRA register is set). 17.8.2 ADC Control and Status Register A - ADCSRA
Bit Read/Write Initial Value 7 ADEN R/W 0 6 ADSC R/W 0 5 ADATE R/W 0 4 ADIF R 0 3 ADIE R/W 0 2 ADPS2 R/W 0 1 ADPS1 R/W 0 0 ADPS0 R/W 0 ADCSRA
* Bit 7 - ADEN: ADC Enable Bit Set this bit to enable the ADC. Clear this bit to disable the ADC. Clearing this bit while a conversion is running will take effect at the end of the conversion. * Bit 6- ADSC: ADC Start Conversion Bit Set this bit to start a conversion in single conversion mode or to start the first conversion in free running mode. Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect. The first conversion performs the initialization of the ADC. * Bit 5 - ADATE: ADC Auto trigger Enable Bit Set this bit to enable the auto triggering mode of the ADC. Clear it to return in single conversion mode. In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB register. See Table 17-6 on page 220. * Bit 4- ADIF: ADC Interrupt Flag Set by hardware as soon as a conversion is complete and the Data register are updated with the conversion result. Cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF can be cleared by writing it to logical one. * Bit 3- ADIE: ADC Interrupt Enable Bit Set this bit to activate the ADC end of conversion interrupt. Clear it to disable the ADC end of conversion interrupt. * Bit 2, 1, 0- ADPS2, ADPS1, ADPS0: ADC Prescaler Selection Bits These 3 bits determine the division factor between the system clock frequency and input clock of the ADC. The different setting are shown in Table 17-5 on page 219.
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Table 17-5.
ADPS2 0 0 0 0 1 1 1 1
ADC Prescaler Selection
ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 Division Factor 2 2 4 8 16 32 64 128
17.8.3
ADC Control and Status Register B- ADCSRB
Bit Read/Write Initial Value 7 ADHSM R/W 0 6 ADNCDIS R/W 0 5 0 4 ADSSEN R/W 0 3 ADTS3 R/W 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB
* Bit 7 - ADHSM: ADC High Speed Mode Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to convert with an ADC clock frequency higher than 200KHz. * Bit 6 - ADNCDIS: ADC Noise Canceller Disable Set this bit to disable automatic ADC start when entering Idle or ADC Noise reduction Modes. Clear it to enable automatic ADC start when entering Idle or ADC reduction Modes.. The ADNCDIS must be set before entering Idle or ADC Noise reduction Modes if the ADC is running or Auto triggered to prevent false ADC restart. * Bit 5 - Reserved * Bit 4 - ADSSEN: ADC Single Shot Enable on PSC's synchronization signals Set this bit to enable single shot mode when auto trigger on PSCRASY & PSC2ASY. In this case a single conversion will be performed and PSCRASY & PSC2ASY will be blocked until ADCH reading. Clear it to enable continuous conversion on PSCRASY & PSC2ASY auto triggering. * Bit 3, 2, 1, 0- ADTS3:ADTS0: ADC Auto Trigger Source Selection Bits These bits are only necessary in case the ADC works in auto trigger mode. It means if ADATE bit in ADCSRA register is set. In accordance with the Table 17-6, these 3 bits select the interrupt event which will generate the trigger of the start of conversion. The start of conversion will be generated by the rising edge of the selected interrupt flag whether the interrupt is enabled or not.
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In case of trig on PSCnASY event, there is no flag. So, if ADSSEN is reset, a conversion will start each time the trig event appears and the previous conversion is completed .. Table 17-6.
ADTS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
ADC Auto Trigger Source Selection
ADTS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ADTS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ADTS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Free Running Mode Analog Comparator 1 External Interrupt Request 0 Timer/Counter1 Overflow Timer/Counter1 Capture Event PSCRASY Event PSC2ASY Event Analog comparator 2 Analog comparator 3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
17.8.4
ADC Result Data Registers - ADCH and ADCL When an ADC conversion is complete, the conversion results are stored in these two result data registers. When the ADCL register is read, the two ADC result data registers can't be updated until the ADCH register has also been read. Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH. Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read ADCH to have the conversion result.
17.8.4.1
ADLAR = 0
Bit 7 ADC7 Read/Write Initial Value R R 0 0 6 ADC6 R R 0 0 5 ADC5 R R 0 0 4 ADC4 R R 0 0 3 ADC3 R R 0 0 2 ADC2 R R 0 0 1 ADC9 ADC1 R R 0 0 0 ADC8 ADC0 R R 0 0 ADCH ADCL
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17.8.4.2 ADLAR = 1
Bit 7 ADC9 ADC1 Read/Write Initial Value R R 0 0 6 ADC8 ADC0 R R 0 0 5 ADC7 R R 0 0 4 ADC6 R R 0 0 3 ADC5 R R 0 0 2 ADC4 R R 0 0 1 ADC3 R R 0 0 0 ADC2 R R 0 0 ADCH ADCL
17.8.5
Digital Input Disable Register 0 - DIDR0
Bit
7 ADC8D AMP3D
6 ADC7D AMP0-D R/W 0
5 ADC5D ACMP2D R/W 0
4
3
2
1
0 ADC0D ACMP1D R/W 0 DIDR0
ADC4D ADC3D ACMP3MD ACMPMD R/W 0 R/W 0
ADC2D ADC1D ACMP2MD R/W 0 R/W 0
Read/Write Initial Value
R/W 0
* Bit 7:0 - ADC7D..ADC0D: AMP0-D and ADC7:0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 17.8.6 Digital Input Disable Register 1- DIDR1
Bit 7 Read/Write Initial Value 0 6 0 5 R/W 0 4 ACMP1MD AMP0+D R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 ADC10D 0 ADC9D DIDR1
* Bit 2:0 - AMP0+D and ADC10:8 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to an analog pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
17.9
Amplifier
The AT90PWM81 features one differential amplified channel with programmable 5, 10, 20, and 40 gain stage. Despite the result is given by the 10 bit ADC, the amplifier has been sized to give a 8bits resolution. The negative input on the amplifier can be internally switched to the analog ground. However, amplifier characteristics are specified with differential inputs. Because the amplifier is a switching capacitor amplifier, it needs to be clocked by a synchronization signal called in this document the amplifier synchronization clock. The amplifier samples the input value at the falling edge of the synchronization signal. This allow to measure analog signals with same period as the synchronization. The maximum clock for the amplifier is 250kHz.
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To ensure an accurate result in case of large voltage change, the amplifier input needs to have a quite stable sampled input value during at least 4 Amplifier synchronization clock periods. Amplified conversions can be synchronized to PSC events (See "Synchronization Source Description in One/Two/Four Ramp Modes" on page 133 and "Synchronization Source Description in Centered Mode" on page 134) or to the internal clock CKADC equal to eighth the ADC clock frequency. In case the synchronization is done by the ADC clock divided by 8, this synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific phase of CKADC2. A conversion initiated by the user (i.e., all single conversions, and the first free running conversion) when CKADC2 is low will take the same amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion initiated by the user when CKADC2 is high will take 14 ADC clock cycles due to the synchronization mechanism. The normal way to use the amplifier is to select a synchronization clock via the AMPxTS1:0 bits in the AMPxCSR register. Then the amplifier can be switched on, and the amplification is done on each synchronization event. The amplification is done independently of the ADC. In order to start an amplified Analog to Digital Conversion on the amplified channel, the ADMUX must be configured as specified on Table 17-4 on page 217. The ADC starting is done by setting the ADSC (ADC Start conversion) bit in the ADCSRB register. Until the conversion is not achieved, it is not possible to start a conversion on another channel.
On AT90PWM81, conversion takes advantage of the amplifier characteristics to ensure minimum conversion time. As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion is started. In order to have a better understanding of the functioning of the amplifier synchronization, a timing diagram example is shown Figure 17-15.
In case the amplifier output is modified during the sample phase of the ADC, the on-going conversion is aborted and restarted as soon as the output of the amplifier is stable as shown Figure 17-16.
The only precaution to take is to be sure that the trig signal (PSC) frequency is lower than ADCclk/4. It is also possible to auto trigger conversion on the amplified channel. In this case, the conversion is started at the next amplifier clock event following the last auto trigger event selected thanks to the ADTS bits in the ADCSRB register. In auto trigger conversion, the free running mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion.
Figure 17-15. Amplifier synchronization timing diagram with change on analog input signal. Figure 17-16. Amplifier synchronization timing diagram: behavior when ADSC is set when theamplifier output is changing.
The block diagram of the two amplifiers is shown on Figure 17-17. 222
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Delta V Signal t be o measured 4th stable sample
PSC Block
PSCn_ASY
AMP LI_clk (Sync Clock)
CK ADC Ampli er Block Ampli er Sample Enable
Ampli er Hold Value Valid sample
ADSC ADC ADC Activity ADC Conv ADC Sam pling ADC Result Rea dy
Signal t be o measured
ADC Conv ADC Sam pling ADC Resu Rea dy
PSC Block
PSCn_ASY
AMP LI_clk (Sync Clock)
CK ADC Ampli er Block Ampli er Sample Enable
Ampli er Hold Value Valid sample
ADSC ADC ADC Activity ADC Conv ADC Sam pling ADC Result Rea dy ADC Sam pling Aborted ADC Conv ADC Sam pling ADC Result Rea dy
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Figure 17-17. Amplifiers block diagram
SAMPLING
AMP0+
+
T oward ADC MUX (AMP0)
AMP0-
00 01 10 11
ADCK/8 PSCRASY PSC2ASY
Sampling Clock
no short AMP0+ GND
AMP0EN
AMP0IS AMP0G1 AMP0G0 AMP0GS AMP0CSR
-
AMP0TS1 AMP0TS0
If APMP0GS bit is set, the AMP0- input is open and PD5/AMP0- pin is free for another use. At the same time the negative input of the Amplifier is internally grounded.
17.10 Amplifier Control Registers
The configuration of the amplifier is controlled via the register AMP0CSR. Then the start of conversion is done via the ADC control and status registers. The conversion result is stored on ADCH and ADCL register which contain respectively the most significant bits and the least significant bits. 17.10.1 Amplifier 0 Control and Status register - AMP0CSR
Bit Read/Write Initial Value 7 AMP0EN R/W 0 6 AMP0IS R/W 0 5 AMP0G1 R/W 0 4 AMP0G0 R/W 0 3 AMP0GS 0 2 0 1 AMP0TS1 R/W 0 0 AMP0TS0 R/W 0 AMP0CSR
* Bit 7 - AMP0EN: Amplifier 0 Enable Bit Set this bit to enable the Amplifier 0. Clear this bit to disable the Amplifier 0. Clearing this bit while a conversion is running will take effect at the end of the conversion. * Bit 6- AMP0IS: Amplifier 0 Input Shunt Set this bit to short-circuit the Amplifier 0 input. If AMP0GS is set, the ground switch is released during shunt of inputs. Clear this bit to normally use the Amplifier 0.
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* Bit 5, 4- AMP0G1, 0: Amplifier 0 Gain Selection Bits These 2 bits determine the gain of the amplifier 0. The different setting are shown in Table 17-7. Table 17-7.
AMP0G1 0 0 1 1
Amplifier 0 Gain Selection
AMP0G0 0 1 0 1 Description Gain 5 Gain 10 Gain 20 Gain 40
To ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite stable input value during at least 4 Amplifier synchronization clock periods. * Bit 3- AMP0GS: Amplifier 0 Ground Select of AMP0 This bit select negative input of the amplifier: Set this bit to ground the Amplifier 0 negative input. Clear this bit to normally use the Amplifier 0 differential input.
* Bit 1, 0- AMP0TS1, AMP0TS0: Amplifier 0 Trigger Source Selection Bits In accordance with the Table 17-8, these 2 bits select the event which will generate the trigger for the amplifier 0. This trigger source is necessary to start the conversion on the amplified channel. Table 17-8.
AMP0TS1 0 0 1 1
AMP0 Auto Trigger Source Selection
AMP0TS0 0 1 0 1 Trig on PSC2ASY Description Auto synchronization on ADC Clock/8 Trig on PSCRASY
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18. Digital to Analog Converter - DAC
18.1 Features
* * * * *
10 bits resolution 8 bits linearity +/- 0.5 LSB accuracy between 100mV and AVcc-100mV Vout = DAC*Vref/1023 The DAC could be connected to the negative inputs of the analog comparators and/or to a dedicated output driver. * Output impedance around 1KOhm.
The AT90PWM81 features a 10-bit Digital to Analog Converter. This DAC can be used for the analog comparators
The DAC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than 0.3V from VCC. See the paragraph "ADC Noise Canceler" on page 209 on how to connect this pin. The reference voltage is the same as the one used for the ADC, See "ADC Multiplexer Register - ADMUX" on page 216.. These nominally 2.56V Vref or AVCC are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance.
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Figure 18-1. Digital to Analog Converter Block Schematic
VRef
DAC
DAC Result
10 1 10 0 10
DAC High bits
DAC Lo bits w
DACH
DACL Update D AC T rigger
Sources
Edge Detector
DAA TE
DATS2
DATS1
DATS0 DACON
-
DALA
DAEN
18.2
Operation
The Digital to Analog Converter generates an analog signal proportional to the value of the DAC registers value. In order to have an accurate sampling frequency control, there is the possibility to update the DAC input values through different trigger events.
18.3
Starting a Conversion
The DAC is configured thanks to the DACON register. As soon as the DAEN bit in DACON register is set, the DAC converts the value present on the DACH and DACL registers in accordance with the register DACON setting. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the DAC Auto Trigger Enable bit, DAATE in DACON. The trigger source is selected by setting the DAC Trigger Select bits, DATS in DACON (See description of the DATS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the DAC converts the value present on the DACH and DACL registers in accordance with the register DACON setting. This provides a method of starting conversions at fixed intervals. If the trigger signal is still set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt flag will be set even if the specific interrupt is
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disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 18.3.1 DAC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the DAC. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF pin. AVCC is connected to the DAC through a passive switch. The internal 2.56V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. When the external AREF pin is connected to the DAC, the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedance voltmeter. Note that VREF is a high impedance source, and only a capacitive load should be connected in a system. The user may switch between AVCC, AVCC and 2.56V as reference selection. The first DAC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
18.4
DAC Register Description
The DAC is controlled via three dedicated registers: * The DACON register which is used for DAC configuration * DACH and DACL which are used to set the value to be converted.
18.4.1
Digital to Analog Conversion Control Register - DACON
Bit Read/Write Initial Value 7 DAATE R/W 0 6 DATS2 R/W 0 5 DATS1 R/W 0 4 DATS0 R/W 0 3 0 2 DALA R/W 0 1 0 0 DAEN R/W 0 DACON
* Bit 7 - DAATE: DAC Auto Trigger Enable bit (not useful, may be left for compatibility) Set this bit to update the DAC input value on the positive edge of the trigger signal selected with the DACTS2-0 bit in DACON register. Clear it to automatically update the DAC input when a value is written on DACH register. * Bit 6:4 - DATS2, DATS1, DATS0: DAC Trigger Selection bits (not useful, may be left for compatibility) These bits are only necessary in case the DAC works in auto trigger mode. It means if DAATE bit is set. In accordance with the Table 18-1, these 3 bits select the interrupt event which will generate the update of the DAC input values. The update will be generated by the rising edge of the selected interrupt flag whether the interrupt is enabled or not. Table 18-1.
DATS2 0 0 0 0
DAC Auto Trigger source selection
DATS1 0 0 1 1 DATS0 0 1 0 1 Description Analog comparator 0 Analog comparator 1 External Interrupt Request 0 Reserved
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Table 18-1.
DATS2 1 1 1 1
DAC Auto Trigger source selection (Continued)
DATS1 0 0 1 1 DATS0 0 1 0 1 Description Reserved Reserved Timer/Counter1 Overflow Timer/Counter1 Capture Event
* Bit 2 - DALA: Digital to Analog Left Adjust Set this bit to left adjust the DAC input data. Clear it to right adjust the DAC input data. The DALA bit affects the configuration of the DAC data registers. Changing this bit affects the DAC output on the next DACH writing. * Bit 1 - Reserved . * Bit 0 - DAEN: Digital to Analog Enable bit Set this bit to enable the DAC, Clear it to disable the DAC. 18.4.2 Digital to Analog Converter input Register - DACH and DACL DACH and DACL registers contain the value to be converted into analog voltage. Writing the DACL register forbid the update of the input value until DACH has not been written too. So the normal way to write a 10-bit value in the DAC register is firstly to write DACL the DACH. In order to work easily with only 8 bits, there is the possibility to left adjust the input value. Like this it is sufficient to write DACH to update the DAC value. 18.4.2.1 DALA = 0
Bit 7 DAC7 Read/Write Initial Value R/W R/W 0 0 6 DAC6 R/W R/W 0 0 5 DAC5 R/W R/W 0 0 4 DAC4 R/W R/W 0 0 3 DAC3 R/W R/W 0 0 2 DAC2 R/W R/W 0 0 1 DAC9 DAC1 R/W R/W 0 0 0 DAC8 DAC0 R/W R/W 0 0 DACH DACL
18.4.2.2
DALA = 1
Bit 7 DAC9 DAC1 Read/Write Initial Value R/W R/W 0 0 6 DAC8 DAC0 R/W R/W 0 0 5 DAC7 R/W R/W 0 0 4 DAC6 R/W R/W 0 0 3 DAC5 R/W R/W 0 0 2 DAC4 R/W R/W 0 0 1 DAC3 R/W R/W 0 0 0 DAC2 R/W R/W 0 0 DACH DACL
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To work with the 10-bit DAC, two registers have to be updated. In order to avoid intermediate value, the DAC input values which are really converted into analog signal are buffering into unreachable registers. In normal mode, the update of the shadow register is done when the register DACH is written. In case DAATE bit is set, the DAC input values will be updated on the trigger event selected through DATS bits. In order to avoid wrong DAC input values, the update can only be done after having written respectively DACL and DACH registers. It is possible to work on 8-bit configuration by only writing the DACH value. In this case, update is done each trigger event. In case DAATE bit is cleared, the DAC is in an automatic update mode. Writing the DACH register automatically update the DAC input values with the DACH and DACL register values. It means that whatever is the configuration of the DAATE bit, changing the DACL register has no effect on the DAC output until the DACH register has also been updated. So, to work with 10 bits, DACL must be written first before DACH. To work with 8-bit configuration, writing DACH allows the update of the DAC.
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19. debugWIRE On-chip Debug System
19.1 Features
* * * * * * * * * *
Complete Program Flow Control Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin Real-time Operation Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs) Unlimited Number of Program Break Points (Using Software Break Points) Non-intrusive Operation Electrical Characteristics Identical to Real Device Automatic Configuration System High-Speed Operation Programming of Non-volatile Memories
19.2
Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow, execute AVR instructions in the CPU and to program the different non-volatile memories.
19.3
Physical Interface
When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wireAND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. Figure 19-1. The debugWIRE Setup
1.8 - 5.5V
VCC
dW
dW(RESET)
GND
Figure 19-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. When designing a system where debugWIRE will be used, the following observations must be made for correct operation:
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* Pull-up resistors on the dW/(RESET) line must not be smaller than 10k. The pull-up resistor is not required for debugWIRE functionality. * Connecting the RESET pin directly to VCC will not work. * Capacitors connected to the RESET pin must be disconnected when using debugWire. * All external reset sources must be disconnected.
19.4
Software Break Points
debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in AVR Studio(R) will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK instruction will be stored. When program execution is continued, the stored instruction will be executed before continuing from the Program memory. A break can be inserted manually by putting the BREAK instruction in the program. The Flash must be re-programmed each time a Break Point is changed. This is automatically handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore reduce the Flash Data retention. Devices used for debugging purposes should not be shipped to end customers.
19.5
Limitations of debugWIRE
The debugWIRE communication pin (dW) is physically located on the same pin as External Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is enabled. The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e., when the program in the CPU is running. When the CPU is stopped, care must be taken while accessing some of the I/O Registers via the debugger (AVR Studio). A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire is not used.
19.6
debugWIRE Related Register in I/O Memory
The following section describes the registers used with the debugWire.
19.6.1
debugWire Data Register - DWDR
Bit Read/Write Initial Value 7 DWDR[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 DWDR
The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations.
20. Boot Loader Support - Read-While-Write Self-Programming
In AT90PWM81, the Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated protocol to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program 232
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code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader memory is configured with fuses and the Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection.
20.1
Boot Loader Features
* * * * * * *
Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support 1. A page is a section in the Flash consisting of several bytes (see Table 21-11 on page 254) used during programming. The page organization does not affect normal operation.
Note:
20.2
Application and Boot Loader Flash Sections
The Flash memory is organized in two main sections, the Application section and the Boot Loader section (see Figure 20-2). The size of the different sections is configured by the BOOTSZ Fuses as shown in Table 20-7 on page 246 and Figure 20-2. These two sections can have different level of protection since they have different sets of Lock bits.
20.2.1
Application Section The Application section is the section of the Flash that is used for storing the application code. The protection level for the Application section can be selected by the application Boot Lock bits (Boot Lock bits 0), see Table 20-2 on page 237. The Application section can never store any Boot Loader code since the SPM instruction is disabled when executed from the Application section. BLS - Boot Loader Section While the Application section is used for storing the application code, the The Boot Loader software must be located in the BLS since the SPM instruction can initiate a programming when executing from the BLS only. The SPM instruction can access the entire Flash, including the BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader Lock bits (Boot Lock bits 1), see Table 20-3 on page 237.
20.2.2
20.3
Read-While-Write and No Read-While-Write Flash Sections
Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configured by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 20-8 on page 246 and Figure 20-2 on page 236. The main difference between the two sections is: * When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation. * When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation.
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Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax "Read-While-Write section" refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update. 20.3.1 RWW - Read-While-Write Section If a Boot Loader software update is programming a page inside the RWW section, it is possible to read code from the Flash, but only code that is located in the NRWW section. During an on-going programming, the software must ensure that the RWW section never is being read. If the user software is trying to read code that is located inside the RWW section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader section. The Boot Loader section is always located in the NRWW section. The RWW Section Busy bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read as logical one as long as the RWW section is blocked for reading. After a programming is completed, the RWWSB must be cleared by software before reading code located in the RWW section. See "Store Program Memory Control and Status Register - SPMCSR" on page 238. for details on how to clear RWWSB. NRWW - No Read-While-Write Section The code located in the NRWW section can be read when the Boot Loader software is updating a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU is halted during the entire Page Erase or Page Write operation. Table 20-1. Read-While-Write Features
Which Section Can be Read During Programming? NRWW Section None Is the CPU Halted? No Yes Read-While-Write Supported? Yes No
20.3.2
Which Section does the Z-pointer Address During the Programming? RWW Section NRWW Section
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Figure 20-1. Read-While-Write vs. No Read-While-Write
Read-While-Write (RWW) Section
Z-pointer Addresses RWW Section
Z-pointer Addresses NRWW Section
No Read-While-Write (NRWW) Section
CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation
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Figure 20-2.
Memory Sections
Program Memory BOOTSZ = '11' 0x0000 Program Memory BOOTSZ = '10' 0x0000
Read-While-Write Section
Read-While-Write Section
Application Flash Section
Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ = '00'
Boot Loader Flash Section
End Application Start Boot Loader Flashend
Program Memory BOOTSZ = '01' 0x0000
Read-While-Write Section Read-While-Write Section
0x0000
Application Flash Section
Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend
No Read-While-Write Section
End RWW, End Application Start NRWW, Start Boot Loader
Boot Loader Flash Section
Flashend
Note:
1. The parameters in the figure above are given in Table 20-7 on page 246.
20.4
Boot Loader Lock Bits
If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: * To protect the entire Flash from a software update by the MCU. * To protect only the Boot Loader Flash section from a software update by the MCU. * To protect only the Application Flash section from a software update by the MCU. * Allow software update in the entire Flash. See Table 20-2 and Table 20-3 for further details. The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction. Sim-
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ilarly, the general Read/Write Lock (Lock Bit mode 1) does not control reading nor writing by LPM/SPM, if it is attempted. Table 20-2.
BLB0 Mode 1 2
Boot Lock Bit0 Protection Modes (Application Section)(1)
BLB02 1 1 BLB01 1 0 Protection No restrictions for SPM or LPM accessing the Application section. SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
3
0
0
4
0
1
Note:
1. "1" means unprogrammed, "0" means programmed
Table 20-3.
BLB1 Mode 1 2
Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)
BLB12 1 1 BLB11 1 0 Protection No restrictions for SPM or LPM accessing the Boot Loader section. SPM is not allowed to write to the Boot Loader section. SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
3
0
0
4
0
1
Note:
1. "1" means unprogrammed, "0" means programmed
20.5
Entering the Boot Loader Program
Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code. Note that the fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 20-4.
BOOTRST 1 0 Note:
Boot Reset Fuse(1)
Reset Address Reset Vector = Application Reset (address 0x0000) Reset Vector = Boot Loader Reset (see Table 20-7 on page 246)
1. "1" means unprogrammed, "0" means programmed
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20.5.1
Store Program Memory Control and Status Register - SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
Bit Read/Write Initial Value 7 SPMIE R/W 0 6 RWWSB R 0 5 SIGRD R/W 0 4 RWWSRE R/W 0 3 BLBSET R/W 0 2 PGWRT R/W 0 1 PGERS R/W 0 0 SPMEN R/W 0 SPMCSR
* Bit 7 - SPMIE: SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is cleared. * Bit 6 - RWWSB: Read-While-Write Section Busy When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated.
* Bit 5 - SIGRD: Signature Row Read If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see Reading the Signature Row from Software243" for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used.
* Bit 4 - RWWSRE: Read-While-Write Section Read Enable When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lost. * Bit 3 - BLBSET: Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See "Reading the Fuse and Lock Bits from Software" on page 242 for details. * Bit 2 - PGWRT: Page Write 238
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If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. * Bit 1 - PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. * Bit 0 - SPMEN: Self Programming Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than "10001", "01001", "00101", "00011" or "00001" in the lower five bits will have no effect.
20.6
Addressing the Flash During Self-Programming
The Z-pointer is used to address the SPM commands.
Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0
Since the Flash is organized in pages (see Table 21-11 on page 254), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is1 shown in Figure 203. Note that the Page Erase and Page Write operations are addressed independently. Therefore it is of major importance that the Boot Loader software addresses the same page in both the Page Erase and Page Write operation. Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other operations. The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits. The content of the Z-pointer is ignored and will have no effect on the operation. The LPM instruction does also use the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
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Figure 20-3.
Addressing the Flash During SPM(1)
BIT 15 ZPCMSB ZPAGEMSB 10 0 PCMSB PROGRAM COUNTER
PCPAGE
Z - REGISTER PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. The different variables used in Figure 20-3 are listed in Table 20-9 on page 247.
20.7
Self-Programming the Flash
The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation: Alternative 1, fill the buffer before a Page Erase * Fill temporary page buffer * Perform a Page Erase * Perform a Page Write Alternative 2, fill the buffer after Page Erase * Perform a Page Erase * Fill temporary page buffer * Perform a Page Write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. See "Simple Assembly Code Example for a Boot Loader" on page 244 for an assembly code example.
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20.7.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write "X0000011" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. * Page Erase to the RWW section: The NRWW section can be read during the Page Erase. * Page Erase to the NRWW section: The CPU is halted during the operation. 20.7.2 Filling the Temporary Buffer (Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write "00000001" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 20.7.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write "X0000101" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. * Page Write to the RWW section: The NRWW section can be read during the Page Write. * Page Write to the NRWW section: The CPU is halted during the operation. 20.7.4 Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in Section "Moving Interrupts Between Application and Boot Space", page 64. Consideration While Updating BLS Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further software updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes. Prevent Reading the RWW Section During Self-Programming During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS as described in Section "Moving Interrupts Between Application and Boot Space", page 64, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See "Simple Assembly Code Example for a Boot Loader" on page 244 for an example.
20.7.5
20.7.6
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20.7.7
Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write "X0001001" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
Bit R0 7 1 6 1 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 1 0 1
See Table 20-2 and Table 20-3 for how the different settings of the Boot Loader bits affect the Flash access. If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer is don't care during this operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the lOck bits). For future compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to "1" when writing the Lock bits. When programming the Lock bits the entire Flash can be read during the operation. 20.7.8 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
Bit Rd 7 - 6 - 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 LB2 0 LB1
20.7.9
The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 21-4 on page 249 for a detailed description and mapping of the Fuse Low byte.
Bit Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to Table 21-5 on page 251 for detailed description and mapping of the Fuse High byte.
Bit Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
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When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to Table 21-4 on page 249 for detailed description and mapping of the Extended Fuse byte.
Bit Rd 7 - 6 - 5 - 4 - 3 EFB3 2 EFB2 1 EFB1 0 EFB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one.
20.7.10
Reading the Signature Row from Software To read the Signature Row from software, load the Z-pointer with the signature byte address given in Table 20-5 and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set in SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will work as described in the "AVR Instruction Set" description. Table 20-5. Signature Row Addressing
Signature Byte Device ID 0, Manufacturer ID OSCAL 8M, RC-OSC calibration Device ID 1, Flash size Reserved Device ID 2, Device Temperature Sensor Offset : TSOFFSET Reserved Temperature Sensor Gain : TSGAIN Lot number at sort, byte 2, ASCII Lot number at sort, Byte 1, ASCII (most left lot#) Lot number at sort, byte 2, ASCII Lot number at sort, Byte 1, ASCII Lot number at sort, byte 2, ASCII Lot number at sort, Byte 1, ASCII Final test Amb VRef : LOW BYTE
(2) (1)
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x0E 0x0F 0x10 0x11 0x12 0x13 0x3C 0x3D 0x3E 0x3F
Data 1EH XXH 93H XXH 88H XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH
Final Test Amb VRef : HIGH BYTE (3) Final Test Hot VRef : LOW BYTE ( only a Read) (4) Final Test Hot VRef : HIGH BYTE( only a Read) (5)
1.TSGAIN typical value is 0x80=128 243
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2.See Note 3
3.Final Test Amb VRef HIGH BYTE and LOW BYTE : Typical values arefor Vref. = 2.56V: HIGH BYTE = 0x0A LOW BYTE = 0x00 This means : Final Test Amb VRef= 0x0A00 = 2560 = Vref. * 1000.
4.See Note 3 which details the value format. 5.See Note 3 which details the value format.
20.7.11
Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. 2. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes.
3.
20.7.12
Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 20-6 shows the typical programming time for Flash accesses from the CPU. Table 20-6. SPM Programming Time
Symbol Flash write (Page Erase, Page Write, and write Lock bits by SPM) Min Programming Time 3.7 ms Max Programming Time 4.5 ms
20.7.13
Simple Assembly Code Example for a Boot Loader
;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20)
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; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-It is assumed that either the interrupt table is moved to the Boot ; loader section or that the interrupts are disabled. .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words .org SMALLBOOTSTART Write_page: ; Page Erase ldi spmcrval, (1<245
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rjmp Return Do_spm: ; check for previous SPM complete Wait_spm: in temp1, SPMCSR sbrc temp1, SPMEN rjmp Wait_spm ; input: spmcrval determines SPM action ; disable interrupts if enabled, store status in temp2, SREG cli ; check that no EEPROM write access is present Wait_ee: sbic EECR, EEPE rjmp Wait_ee ; SPM timed sequence out SPMCSR, spmcrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret
20.7.14
Boot Loader Parameters In Table 20-7 through Table 20-9, the parameters used in the description of the self programming are given. Table 20-7. Boot Size Configuration
Application Flash Section 0x000 - 0xF7F 0x000 - 0xEFF 0x000 - 0xDFF 0x000 - 0xBFF Boot Loader Flash Section 0xF80 0xFFF 0xF00 0xFFF 0xE00 0xFFF 0xC00 0xFFF End Application Section 0xF7F 0xEFF 0xDFF 0xBFF Boot Reset Address (Start Boot Loader Section) 0xF80 0xF00 0xE00 0xC00
BOOTSZ1 1 1 0 0
BOOTSZ0 1 0 1 0
Boot Size 128 words 256 words 512 words 1024 words
Pages 4 8 16 32
Note:
The different BOOTSZ Fuse configurations are shown in Figure 20-2.
Table 20-8.
Section
Read-While-Write Limit
Pages 96 32 Address 0x000 - 0xBFF 0xC00 - 0xFFF
Read-While-Write section (RWW) No Read-While-Write section (NRWW)
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For details about these two section, see "NRWW - No Read-While-Write Section" on page 234 and "RWW - Read-While-Write Section" on page 234 Table 20-9.
Variable PCMSB 11
Explanation of Different Variables used in Figure 20-3 and the Mapping to the Z-pointer
Corresponding Z-value(1) Description Most significant bit in the Program Counter. (The Program Counter is 12 bits PC[11:0]) Most significant bit which is used to address the words within one page (32 words in a page requires 5 bits PC [4:0]). Z12 Z5 PC[11:5] Z12:Z6 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1. Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1. Program counter page address: Page select, for page erase and page write Program counter word address: Word select, for filling temporary buffer (must be zero during page write operation)
PAGEMSB
4
ZPCMSB ZPAGEMSB PCPAGE
PCWORD
PC[4:0]
Z5:Z1
Note:
1. Z15:Z13: always ignored Z0: should be zero for all SPM commands, byte select for the LPM instruction. See "Addressing the Flash During Self-Programming" on page 239 for details about the use of Zpointer during Self-Programming.
21. Memory Programming
21.1 Program And Data Memory Lock Bits
The AT90PWM81 provides six Lock bits which can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional features listed in Table 21-2. The Lock bits can only be erased to "1" with the Chip Erase command. Table 21-1. Lock Bit Byte(1)
Bit No 7 6 BLB12 BLB11 BLB02 BLB01 LB2 LB1 5 4 3 2 1 0 Description - - Boot Lock bit Boot Lock bit Boot Lock bit Boot Lock bit Lock bit Lock bit Default Value 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed)
Lock Bit Byte
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Notes:
1. "1" means unprogrammed, "0" means programmed.
Table 21-2.
Lock Bit Protection Modes(1)(2)
Protection Type LB1 1 0 No memory lock features enabled. Further programming of the Flash and EEPROM is disabled in Parallel and Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode.(1) Further programming and verification of the Flash and EEPROM is disabled in Parallel and Serial Programming mode. The Boot Lock bits and Fuse bits are locked in both Serial and Parallel Programming mode.(1)
Memory Lock Bits LB Mode 1 2 LB2 1 1
3
0
0
Notes:
1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2. 2. "1" means unprogrammed, "0" means programmed
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Table 21-3.
BLB0 Mode 1 2
Lock Bit Protection Modes(1)(2). Only ATmega88/168.
BLB02 1 1 BLB01 1 0 No restrictions for SPM or LPM accessing the Application section. SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
3
0
0
4
0
1
BLB1 Mode 1 2
BLB12 1 1
BLB11 1 0 No restrictions for SPM or LPM accessing the Boot Loader section. SPM is not allowed to write to the Boot Loader section. SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
3
0
0
4
0
1
Notes:
1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2. 2. "1" means unprogrammed, "0" means programmed
21.2
Fuse Bits
The AT90PWM81 has three Fuse bytes. Table 21-4 - Table 21-6 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, "0", if they are programmed.
Table 21-4.
Extended Low Fuse Byte
Bit No 7 6 5 4 3 Description PSC2 Reset Behavior PSC2 Reset Behavior for OUT22 & 23 PSC Reduced Reset Behavior PSCOUT & PSCOUTR Reset Value PSC & PSCR Inputs Reset Behavior Default Value 1 1 1 1 1
Extended Fuse Byte PSC2RB PSC2RBA PSCRRB PSCRV PSCINRB
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Table 21-4.
Extended Low Fuse Byte
Bit No 2 1 0 Description Brown-out Detector trigger level Brown-out Detector trigger level Brown-out Detector trigger level Default Value 1 (unprogrammed) 0 (programmed) 1 (unprogrammed)
(1)
Extended Fuse Byte BODLEVEL2
BODLEVEL1(1) BODLEVEL0(1) Notes:
1. See Table 7-2 on page 52 for BODLEVEL Fuse decoding
21.2.1
PSC Output Behavior During Reset For external component safety reason, the state of PSC outputs during Reset can be programmed by fuses PSCRV, PSCRRB & PSC2RB. These fuses are located in the Extended Fuse Byte ( see Table 21-4) PSCRV gives the state low or high which will be forced on PSC outputs selected by PSC0RB & PSC2RB fuses. If PSCRV fuse equals 0 (programmed), the selected PSC outputs will be forced to low state. If PSCRV fuse equals 1 (unprogrammed), the selected PSC outputs will be forced to high state. If PSCRRB fuse equals 1 (unprogrammed), PSCOUTR0 & PSCOUTR1 keep a standard port behavior. If PSC0RB fuse equals 0 (programmed), PSCOUTR0 & PSCOUTR1 are forced at reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUTR0 & PSCOUTR1 keep the forced state until PSOC0 register is written. If PSC2RB fuse equals 1 (unprogrammed), PSCOUT20 & PSCOUT21 keep a standard port behavior. If PSC2RB fuse equals 0 (programmed), PSCOUT20 & PSCOUT21 are forced at reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUT20 & PSCOUT21 keep the forced state until PSOC2 register is written. If PSC2RBA fuse equals 1 (unprogrammed), PSCOUT22 & PSCOUT23 keep a standard port behavior. If PSC2RBA fuse equals 0 (programmed), PSCOUT22 & PSCOUT23 are forced at reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUT22 & PSCOUT23 keep the forced state until PSOC2 register is written.
21.2.2
PSC Input Behavior During Reset For power consumption under reset reason, the state of PSC & PSCR inputs during Reset can be programmed by fuse PSCINRB. If PSCINRB fuse equals 1 (unprogrammed), PSC & PSCR input keep a standard port behavior. If PSCINRB fuse equals 0 (programmed), PSC & PSCR input pull-up are forced while the reset is active. Affected pins are PSCIN2, PSCINr, PSCIN2A, PSCINrA. To prevent any conflict on PD1, this fuse has no effect on PSCINrB.
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Table 21-5.
RSTDISBL(1) DWEN SPIEN(2) WDTON(3) EESAVE BOOTSZ1 BOOTSZ0 BOOTRST Notes:
Fuse High Byte
Bit No 7 6 5 4 3 2 1 0 Description External Reset Disable debugWIRE Enable Enable Serial Program and Data Downloading Watchdog Timer Always On EEPROM memory is preserved through the Chip Erase Select Boot Size (see Table 113 for details) Select Boot Size (see Table 113 for details) Select Reset Vector Default Value 1 (unprogrammed) 1 (unprogrammed) 0 (programmed, SPI programming enabled) 1 (unprogrammed) 1 (unprogrammed), EEPROM not reserved 0 (programmed)(4) 0 (programmed)(4) 1 (unprogrammed)
High Fuse Byte
1. See "Alternate Functions of Port E" on page 78 for description of RSTDISBL Fuse. 2. The SPIEN Fuse is not accessible in serial programming mode. 3. See "Watchdog Timer Configuration" on page 59 for details. 4. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 21-7 on page 253 for details.
Table 21-6.
Low Fuse Byte CKDIV8(4) CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0
(3)
Fuse Low Byte
Bit No 7 6 5 4 3 2 1 0 Description Divide clock by 8 Clock output Select start-up time Select start-up time Select Clock source Select Clock source Select Clock source Select Clock source Default Value 0 (programmed) 1 (unprogrammed) 1 (unprogrammed)(1) 0 (programmed)(1) 0 (programmed)(2) 0 (programmed)(2) 1 (unprogrammed)(2) 0 (programmed)(2)
Note:
1. The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 5-4 on page 30 for details. 2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 5-1 on page 28 for details. 3. The CKOUT Fuse allows the system clock to be output on PORTD0. See "Clock Output Buffer" on page 34 for details. 4. See "System Clock Prescaler" on page 38 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
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21.2.3
Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode.
21.3
Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space, the signature row.
21.3.1
Signature Bytes For the AT90PWM81 the signature bytes are: 1. 2. 3. 0x000: 0x1E (indicates manufactured by Atmel). 0x002: 0x93 (indicates 8KB Flash memory). 0x004: 0x88 (indicates AT90PWM81 device when 0x002 is 0x93).
21.4
Calibration Byte
The AT90PWM81 has a byte calibration value for the internal RC Oscillator. This byte resides in the byte of address 0x003 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator.
21.5
Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the AT90PWM81. Pulses are assumed to be at least 250 ns unless otherwise noted.
21.5.1
Signal Names In this section, some pins of the AT90PWM81 are referenced by signal names describing their functionality during parallel programming, see Figure 21-1 and Table 21-7. Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 21-9. When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 21-10.
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Figure 21-1. Parallel Programming
+ 5V RDY/BSY OE WR AREF VCC PD2 PD1 AVCC XA0 XA1/BS2 PAGEL/BS1 + 12 V PD5 PD6 PE 2 RESET/PE0 PB[7:0] DATA + 5V
XTAL1/PE1 GND
Table 21-7.
Pin Name Mapping
Pin Name AREF PD2 PD1 PD5 PD6 I/O O I I I I Function 0: Device is busy programming, 1: Device is ready for new command Output Enable (Active low) Write Pulse (Active low) XTAL Action Bit 0 XTAL Action Bit 1 Byte Select 2 ("0" selects Low byte, "1" selects 2'nd High byte) Program memory and EEPROM Data Page Load Byte Select 1 ("0" selects Low byte, "1" selects High byte) Bi-directional Data bus (Output when OE is low)
Signal Name in Programming Mode RDY/BSY OE WR XA0 XA1/BS2
PAGEL/BS1 DATA
PE2 PB[7:0]
I I/O
Table 21-8.
Pin Values Used to Enter Programming Mode
Pin XA1/BS2 XA0 OE WR Symbol Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] Value 0 0 0 0
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Table 21-9.
XA1 0 0 1 1
XA1 and XA0 Coding
XA0 0 1 0 1 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1). Load Data (High or Low data byte for Flash determined by BS1). Load Command No Action, Idle
Table 21-10.
Command Byte Bit Coding
Command Executed Chip Erase Write Fuse bits Write Lock bits Write Flash Write EEPROM Read Signature Bytes and Calibration byte Read Fuse and Lock bits Read Flash Read EEPROM
Command Byte 1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011
Table 21-11.
Device AT90PWM81
No. of Words in a Page and No. of Pages in the Flash
Flash Size 4K words (8K bytes) Page Size 32 words PCWORD PC[4:0] No. of Pages 128 PCPAGE PC[11:5] PCMSB 11
Table 21-12.
Device AT90PWM81
No. of Words in a Page and No. of Pages in the EEPROM
EEPROM Size 512 bytes Page Size 4 bytes PCWORD EEA[1:0] No. of Pages 128 PCPAGE EEA[8:2] EEAMSB 8
21.6
Serial Programming Pin Mapping
Table 21-13. Pin Mapping Serial Programming
Pins I/O I O I Description Serial Data in Serial Data out Serial Clock
Symbol MOSI MISO SCK
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21.7
21.7.1
Parallel Programming
Enter Programming Mode The following algorithm puts the device in Parallel (High-voltage) > Programming mode: 1. 2. 3. 4. 5. 6. Set Prog_enable pins listed in Table 21-8. to "0000", RESET pin to "0" and Vcc to 0V. Apply 4.5 - 5.5V between VCC and GND. Ensure that Vcc reaches at least 1.8V within the next 20s. Wait 20 - 60s, and apply 11.5 - 12.5V to RESET. Keep the Prog_enable pins unchanged for at least 10s after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. Wait at least 300s before giving any parallel programming commands. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
If the rise time of the Vcc is unable to fulfill the requirements listed above, the following alternative algorithm can be used. 1. 2. 3. 4. 5. 6. 21.7.2 Set Prog_enable pins listed in Table 21-8. to "0000", RESET pin to "0" and Vcc to 0V. Apply 4.5 - 5.5V between VCC and GND. Monitor Vcc, and as soon as Vcc reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET. Keep the Prog_enable pins unchanged for at least 10s after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. Wait until Vcc actually reaches 4.5 -5.5V before giving any parallel programming commands. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. * The command needs only be loaded once when writing or reading multiple memory locations. * Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. * Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading.
21.7.3
Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed.
Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Load Command "Chip Erase" 1. 2. 3. 4. 5. 6. Set XA1, XA0 to "10". This enables command loading. Set BS1 to "0". Set DATA to "1000 0000". This is the command for Chip Erase. Give XTAL1 a positive pulse. This loads the command. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. Wait until RDY/BSY goes high before loading a new command.
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21.7.4
Programming the Flash The Flash is organized in pages, see Table 21-11 on page 254. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command "Write Flash" 1. 2. 3. 4. Set XA1, XA0 to "10". This enables command loading. Set BS1 to "0". Set DATA to "0001 0000". This is the command for Write Flash. Give XTAL1 a positive pulse. This loads the command.
B. Load Address Low byte 1. 2. 3. 4. Set XA1, XA0 to "00". This enables address loading. Set BS1 to "0". This selects low address. Set DATA = Address low byte (0x00 - 0xFF). Give XTAL1 a positive pulse. This loads the address low byte.
C. Load Data Low Byte 1. 2. 3. Set XA1, XA0 to "01". This enables data loading. Set DATA = Data low byte (0x00 - 0xFF). Give XTAL1 a positive pulse. This loads the data byte.
D. Load Data High Byte 1. 2. 3. 4. Set BS1 to "1". This selects high data byte. Set XA1, XA0 to "01". This enables data loading. Set DATA = Data high byte (0x00 - 0xFF). Give XTAL1 a positive pulse. This loads the data byte.
E. Latch Data 1. 2. Set BS1 to "1". This selects high data byte. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 21-3 for signal waveforms)
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 21-2 on page 257. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. G. Load Address High byte 1. 2. 3. 4. Set XA1, XA0 to "00". This enables address loading. Set BS1 to "1". This selects high address. Set DATA = Address high byte (0x00 - 0xFF). Give XTAL1 a positive pulse. This loads the address high byte.
H. Program Page 1. 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. Wait until RDY/BSY goes high (See Figure 21-3 for signal waveforms).
I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. 256
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J. End Page Programming 1. 2. 3. 1. Set XA1, XA0 to "10". This enables command loading. Set DATA to "0000 0000". This is the command for No Operation. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Addressing the Flash Which is Organized in Pages(1)
PCMSB PROGRAM COUNTER
PCPAGE
Figure 21-2.
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. PCPAGE and PCWORD are listed in Table 21-11 on page 254.
Figure 21-3.
Programming the Flash Waveforms(1)
F
A
DATA 0x10
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
XA1/BS2
XA0
PAGEL/BS1
XTAL1
WR
RDY/BSY
RESET +12V OE
Note:
1. "XX" is don't care. The letters refer to the programming description above.
21.7.5
Programming the EEPROM The EEPROM is organized in pages, see Table 21-12 on page 254. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to "Programming the Flash" on page 256 for details on Command, Address and Data loading):
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1. 2. 3. 4. 5.
A: Load Command "0001 0001". G: Load Address High Byte (0x00 - 0xFF). B: Load Address Low Byte (0x00 - 0xFF). C: Load Data (0x00 - 0xFF). E: Latch data (give PAGEL a positive pulse).
K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. 2. 3. Set BS1 to "0". Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. Wait until to RDY/BSY goes high before programming the next page (See Figure 21-4 for signal waveforms). Programming the EEPROM Waveforms
K
Figure 21-4.
A
DATA 0x11
G
ADDR. HIGH
B
ADDR. LOW
C
DATA
E
XX
B
ADDR. LOW
C
DATA
E
XX
L
XA1/BS2
XA0
PAGEL/BS1
XTAL1
WR
RDY/BSY
RESET +12V OE
21.7.6
Reading the Flash The algorithm for reading the Flash memory is as follows (refer to "Programming the Flash" on page 256 for details on Command and Address loading): 1. 2. 3. 4. 5. 6. A: Load Command "0000 0010". G: Load Address High Byte (0x00 - 0xFF). B: Load Address Low Byte (0x00 - 0xFF). Set OE to "0", and BS1 to "0". The Flash word low byte can now be read at DATA. Set BS1 to "1". The Flash word high byte can now be read at DATA. Set OE to "1".
21.7.7
Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to "Programming the Flash" on page 256 for details on Command and Address loading): 1. 2. 3. A: Load Command "0000 0011". G: Load Address High Byte (0x00 - 0xFF). B: Load Address Low Byte (0x00 - 0xFF).
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4. 5. 21.7.8 Set OE to "0", and BS1 to "0". The EEPROM Data byte can now be read at DATA. Set OE to "1".
Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to "Programming the Flash" on page 256 for details on Command and Data loading): 1. 2. 3. A: Load Command "0100 0000". C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. Give WR a negative pulse and wait for RDY/BSY to go high.
21.7.9
Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to "Programming the Flash" on page 256 for details on Command and Data loading): 1. 2. 3. 4. 5. A: Load Command "0100 0000". C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. Set BS1 to "1" and BS2 to "0". This selects high data byte. Give WR a negative pulse and wait for RDY/BSY to go high. Set BS1 to "0". This selects low data byte.
21.7.10
Programming the Extended Fuse Bits The algorithm for programming the Extended Fuse bits is as follows (refer to "Programming the Flash" on page 256 for details on Command and Data loading): 1. 2. 3. 4. 5. 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Set BS1 to "0" and BS2 to "1". This selects extended data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2 to "0". This selects low data byte. Programming the FUSES Waveforms
Write Fuse Low byte A
DATA
0x40
Figure 21-5.
Write Fuse high byte A C
DATA XX
Write Extended Fuse byte A
0x40
C
DATA XX
C
DATA XX
0x40
XA1/BS2
XA0
PAGEL/BS1
XTAL1
WR
RDY/BSY
RESET +12V OE
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21.7.11
Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to "Programming the Flash" on page 256 for details on Command and Data loading): 1. 2. A: Load Command "0010 0000". C: Load Data Low Byte. Bit n = "0" programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. Give WR a negative pulse and wait for RDY/BSY to go high.
3.
The Lock bits can only be cleared by executing Chip Erase. 21.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming the Flash" on page 256 for details on Command loading): 1. 2. 3. 4. 5. 6. A: Load Command "0000 0100". Set OE to "0", BS2 to "0" and BS1 to "0". The status of the Fuse Low bits can now be read at DATA ("0" means programmed). Set OE to "0", BS2 to "1" and BS1 to "1". The status of the Fuse High bits can now be read at DATA ("0" means programmed). Set OE to "0", BS2 to "1", and BS1 to "0". The status of the Extended Fuse bits can now be read at DATA ("0" means programmed). Set OE to "0", BS2 to "0" and BS1 to "1". The status of the Lock bits can now be read at DATA ("0" means programmed). Set OE to "1". Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
Fuse Low Byte 0
Figure 21-6.
0 Extended Fuse Byte BS2 Lock Bits 0 1 1 DATA
Fuse High Byte BS2
1
BS1
21.7.13
Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to "Programming the Flash" on page 256 for details on Command and Address loading): 1. 2. 3. 4. A: Load Command "0000 1000". B: Load Address Low Byte (0x00 - 0x02). Set OE to "0", and BS1 to "0". The selected Signature byte can now be read at DATA. Set OE to "1".
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21.7.14 Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to "Programming the Flash" on page 256 for details on Command and Address loading): 1. 2. 3. 4. A: Load Command "0000 1000". B: Load Address Low Byte, 0x00. Set OE to "0", and BS1 to "1". The Calibration byte can now be read at DATA. Set OE to "1".
2.
21.8
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 21-13 on page 254, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. Figure 21-7. Serial Programming and Verify(1)
+1.8 - 5.5V VCC +1.8 - 5.5V(2) MOSI_A MISO_A SCK_A XTAL1 AVCC
RESET
GND
Notes:
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 21.8.1 Serial Programming Algorithm When writing serial data to the AT90PWM81, data is clocked on the rising edge of SCK.
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When reading data from the AT90PWM81, data is clocked on the falling edge of SCK. See Figure 21-8 for timing details. To program and verify the AT90PWM81 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 21-15): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 21-14.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 21-14.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. At the end of the programming session, RESET can be set high to commence normal operation. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off.
2. 3.
4.
5.
6. 7. 8.
21.8.2
Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See Table 21-14 for tWD_FLASH value. Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the pro-
21.8.3
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grammed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re-programmed without chip erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least t WD_EEPROM before programming the next byte. See Table 21-14 for tWD_EEPROM value. Table 21-14.
Symbol tWD_FLASH tWD_EEPROM tWD_ERASE
Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Minimum Wait Delay 4.5 ms 3.6 ms 9.0 ms
Figure 21-8.
Serial Programming Waveforms
MSB LSB
SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK)
SAMPLE
MSB
LSB
Table 21-15.
Serial Programming Instruction Set
Instruction Format
Instruction Programming Enable Chip Erase Read Program Memory
Byte 1 1010 1100 1010 1100 0010 H000 0100 H000
Byte 2 0101 0011 100x xxxx 000a aaaa 000x xxxx
Byte 3 xxxx xxxx xxxx xxxx bbbb bbbb xxbb bbbb
Byte4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii
Operation Enable Serial Programming after RESET goes low. Chip Erase EEPROM and Flash. Read H (high or low) data o from Program memory at word address a:b. Write H (high or low) data i to Program Memory page at word address b. Data low byte must be loaded before Data high byte is applied within the same address. Write Program Memory Page at address a:b. Read data o from EEPROM memory at address a:b. Write data i to EEPROM memory at address a:b. Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page.
Load Program Memory Page
Write Program Memory Page Read EEPROM Memory Write EEPROM Memory Load EEPROM Memory Page (page access)
0100 1100 1010 0000 1100 0000 1100 0001
000a aaaa 000x xxaa 000x xxaa 0000 0000
bbxx xxxx bbbb bbbb bbbb bbbb 0000 00bb
xxxx xxxx oooo oooo iiii iiii iiii iiii
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Table 21-15.
Serial Programming Instruction Set (Continued)
Instruction Format
Instruction Write EEPROM Memory Page (page access) Read Lock bits
Byte 1 1100 0010 0101 1000
Byte 2 00xx xxaa 0000 0000
Byte 3 bbbb bb00 xxxx xxxx
Byte4 xxxx xxxx xxoo oooo
Operation Write EEPROM page at address a:b. Read Lock bits. "0" = programmed, "1" = unprogrammed. See Table 21-1 on page 247 for details. Write Lock bits. Set bits = "0" to program Lock bits. See Table 21-1 on page 247 for details. Read Signature Byte o at address b. Set bits = "0" to program, "1" to unprogram. See Table XXX on page XXX for details. Set bits = "0" to program, "1" to unprogram. See Table 21-5 on page 251 for details. Set bits = "0" to program, "1" to unprogram. See Table 21-4 on page 249 for details. Read Fuse bits. "0" = programmed, "1" = unprogrammed. See Table XXX on page XXX for details. Read Fuse High bits. "0" = pro-grammed, "1" = unprogrammed. See Table 21-5 on page 251 for details. Read Extended Fuse bits. "0" = programmed, "1" = unprogrammed. See Table 21-4 on page 249 for details. Read Calibration Byte If o = "1", a programming operation is still busy. Wait until this bit returns to "0" before applying another command.
1010 1100 Write Lock bits Read Signature Byte Write Fuse bits 1010 1100 Write Fuse High bits 1010 1100 Write Extended Fuse Bits 0101 0000 Read Fuse bits 0101 1000 Read Fuse High bits 0101 0000 Read Extended Fuse Bits Read Calibration Byte Poll RDY/BSY Note: 0011 1000 1111 0000 0011 0000 1010 1100
111x xxxx
xxxx xxxx
11ii iiii
000x xxxx 1010 0000
xxxx xxbb xxxx xxxx
oooo oooo iiii iiii
1010 1000
xxxx xxxx
iiii iiii
1010 0100
xxxx xxxx
xxxx xxii
0000 0000
xxxx xxxx
oooo oooo
0000 1000
xxxx xxxx
oooo oooo
0000 1000
xxxx xxxx
oooo oooo
000x xxxx 0000 0000
0000 0000 xxxx xxxx
oooo oooo xxxx xxxo
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don't care
21.8.4
SPI Serial Programming Characteristics For characteristics of the SPI module see "SPI Serial Programming Characteristics" on page 264.
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22. Electrical Characteristics(1)
22.1 Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature............................................ -40C to +105C Or Operating Temperature ...................................... -40C to +125C Storage Temperature ............................................... -65C to +150C Voltage on any Pin except RESET with respect to Ground .........................................-1.0V to VCC+0.5V Voltage on RESET with respect to Ground.............. -1.0V to +13.0V Maximum Operating Voltage ......................................................6.0V DC Current per I/O Pin .........................................................40.0 mA DC Current VCC and GND Pins .........................................200.0 mA Note:
1. Electrical Characteristics for this product have not yet been finalized. Please consider all values listed herein as preliminary and non-contractual.
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22.2
DC Characteristics
TA = -40C to +105C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol VIL VIH VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 VOL Parameter Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage (Port B & D and XTAL1, XTAL2 pins as I/O) Output High Voltage(4) (Port B & D and XTAL1, XTAL2 pins as I/O) Output Low Voltage(3) (RESET pin as I/O) Output High Voltage(4) (RESET pin as I/O) Input Leakage Current I/O Pin Input Leakage Current I/O Pin Reset Pull-up Resistor I/O Pin Pull-up Resistor
(3)
Condition Port B & D and XTAL1, XTAL2 pins as I/O Port B D and XTAL1, XTAL2 pins as I/O XTAL1 pin , External Clock Selected XTAL1 pin , External Clock Selected RESET pin RESET pin RESET pin as I/O RESET pin as I/O IOL = 10 mA, VCC = 5V IOL = 5 mA, VCC = 3V IOH = -10 mA, VCC = 5V IOH = -5 mA, VCC = 3V IOL = 2.1 mA, VCC = 5V IOL = 0.8 mA, VCC = 3V IOH = -0.6 mA, VCC = 5V IOH = -0.4 mA, VCC = 3V VCC = 5.5V, pin low (absolute value) VCC = 5.5V, pin high (absolute value)
Min. -0.5 0.6VCC(2) -0.5 0.7VCC(2) -0.5 0.9VCC(2) -0.5 0.8VCC(2)
Typ.
Max. 0.2VCC(1) VCC+0.5 0.1VCC(1) VCC+0.5 0.2VCC(1) VCC+0.5 0.2VCC(1) VCC+0.5 0.6 0.5
Units V V V V V V V V V V V V
VOH
4.3 2.5 0.7 0.5 3.8 2.2 1 1 30 20 200 50
VOL3 VOH3 IIL IIH RRST Rpu
V V V V A A k k
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TA = -40C to +105C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)
Symbol Parameter Condition Active 8 MHz, VCC = 3V, RC osc, , @25C, PRR = 0xFF Active 16 MHz, VCC = 5V, Ext Clock, , @25C, PRR = 0xFF Idle 8 MHz, VCC = 3V, RC Osc, @25C Idle 16 MHz, VCC = 5V, Ext Clock, @25C WDT enabled, VCC = 3V 25C WDT enabled, VCC = 3V 105C WDT enabled, VCC = 5V 25C WDT enabled, VCC = 5V 105C WDT disabled, VCC = 3V 25C WDT disabled, VCC = 3V 105C WDT disabled, VCC = 5V 25C WDT disabled, VCC = 5V 105C VREF Internal voltage reference(7) Analog Comparator input common mode range Input offset voltage 0.110.5
15
mA
Power Supply Current
1.5 4.5 7
2 7
mA mA A
ICC
30 A
Power-down mode(5)
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TA = -40C to +125C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)
Symbol VIL VIH VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 VOL Parameter Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage(3) (Port B & D and XTAL1, XTAL2 pins as I/O) Output High Voltage(4) (Port B & D and XTAL1, XTAL2 pins as I/O) Output Low Voltage(3) (RESET pin as I/O) Output High Voltage(4) (RESET pin as I/O) Input Leakage Current I/O Pin Input Leakage Current I/O Pin Reset Pull-up Resistor I/O Pin Pull-up Resistor Condition Port B & D and XTAL1, XTAL2 pins as I/O Port B D and XTAL1, XTAL2 pins as I/O XTAL1 pin , External Clock Selected XTAL1 pin , External Clock Selected RESET pin RESET pin RESET pin as I/O RESET pin as I/O IOL = 10 mA, VCC = 5V IOL = 5 mA, VCC = 3V IOH = -10 mA, VCC = 5V IOH = -5 mA, VCC = 3V IOL = 2.1 mA, VCC = 5V IOL = 0.8 mA, VCC = 3V IOH = -0.6 mA, VCC = 5V IOH = -0.4 mA, VCC = 3V VCC = 5.5V, pin low (absolute value) VCC = 5.5V, pin high (absolute value) 30 20 3.8 2.2 1 1 200 50 4.3 2.5 0.7 0.5 Min. -0.5 0.6VCC(2) -0.5 0.7VCC(2) -0.5 0.9VCC(2) -0.5 0.8VCC(2) Typ. Max. 0.2VCC(1) VCC+0.5 0.1VCC(1) VCC+0.5 0.2VCC(1) VCC+0.5 0.2VCC(1) VCC+0.5 0.6 0.5 Units V V V V V V V V V V V V V V V V A A k k
VOH
VOL3 VOH3 IIL IIH RRST Rpu
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Symbol Parameter Condition Active 8 MHz, VCC = 3V, RC osc, PRR = 0xFF Active 16 MHz, VCC = 5V, Ext Clock, PRR = 0xFF Power Supply Current Idle 8 MHz, VCC = 3V, RC Osc, @25C Idle 16 MHz, VCC = 5V, Ext Clock, @25C WDT enabled, VCC = 3V 25C WDT enabled, VCC = 3V 105C WDT enabled, VCC = 3V 125C WDT enabled, VCC = 5V 25C ICC WDT enabled, VCC = 5V 105C WDT enabled, VCC = 5V 125C WDT disabled, VCC = 3V 25C WDT disabled, VCC = 3V 105C WDT disabled, VCC = 3V 125C WDT disabled, VCC = 5V 25C WDT disabled, VCC = 5V 105C WDT disabled, VCC = 5V 125C VREF Internal voltage reference(7) Analog Comparator input common mode range Input offset voltage 0.1Power-down mode
(5)
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Symbol IACLK tACID
Parameter Analog Comparator Input Leakage Current Analog Comparator Propagation Delay
Condition VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 5.0V
Min. -50
Typ.
Max. 50
Units nA ns
50 (6)
Note:
1. "Max" means the highest value where the pin is guaranteed to be read as low 2. "Min" means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: SO20 and TQFN Package: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports B6 - B7, D0 - D3, E0 should not exceed 100 mA. 3] The sum of all IOL, for ports B0 - B1, D4, E1 - E2 should not exceed 100 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: SO20 and TQFN Package: 1] The sum of all IOH, for all ports, should not exceed 400 mA. 2] The sum of all IOH, for ports B6 - B7, D0 - D3, E0 should not exceed 150 mA. 3] The sum of all IOH, for ports B0 - B1, D4, E1 - E2 should not exceed 150 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.5V. 6. Propagation delay of the internal comparator with 100mV overdrive condition. 7. accuracy : 8% from -40C to +125C
22.3
22.3.1
Clock Drive Characteristics
Calibrated Internal RC Oscillator Accuracy Calibration Accuracy of Internal RC Oscillator
Frequency VCC 3V 2.7V - 5.5V 2.7V - 5.5V Temperature 25C -40C +105 or 125C -40C +105 or 125C Calibration Accuracy 1% 6% 5%
Table 22-1.
Factory Calibration Factory Calibration User Calibration
8.0 MHz 8.0 MHz 7.6 - 8.4 MHz
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22.3.2 Watchdog Oscillator Accuracy Accuracy of Watchdog Oscillator
Calibration Accuracy 40%
Table 22-2.
Frequency 128 kHz
22.3.3
External Clock Drive Waveforms Figure 22-1. External Clock Drive Waveforms
V IH1 V IL1
22.3.4
External Clock Drive
Table 22-3.
External Clock Drive
VCC=2.7-5.5V VCC=4.5-5.5V Min. 0 62 20 20 1.6 1.6 2 0.5 0.5 2 Max. 16 Units MHz ns ns ns s s %
Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL
Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Change in period from one clock cycle to the next
Min. 0 83 30 30
Max. 12
tCLCL
22.4
Maximum Speed vs. VCC
Maximum frequency is depending on VCC. As shown in Figure 22-2 , the Maximum Frequency equals 12MHz when VCC is contained between 2.7V and 4.5V and equals 16Mhz when VCC is contained between 4.5V and 5.5V.
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Figure 22-2.
Maximum Frequency vs. VCC, AT90PWM81
16Mhz
12Mhz
8Mhz Safe Operating Area
2.7V
4.5V
5.5V
22.5
PLL Characteristics
. Table 22-4.
Symbol PLLIF PLLF PLLLT 1. 2.
PLL Characteristics - VCC = 2.7V to 5.5V (unless otherwise noted)
Parameter Input Frequency PLL Factor Lock-in Time
(1)
Min.
Typ. 8
Max.
Units MHz
4
8
(2)
64
S
While connected to external clock or external oscillator, PLL Input Frequency must be selected to provide outputs with frequency in accordance with driven parts of the circuit (CPU core, PSC... When Vcc is below 4.5V, Max. PLLF is 6.
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22.6 SPI Timing Characteristics
See Figure 22-3 and Figure 22-4 for details. Table 22-5. SPI Timing Parameters
Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Note: SCK period SCK high/low Rise/Fall time Setup Hold Out to SCK SCK to out SCK to out high SS low to out SCK period SCK high/low (1) Rise/Fall time Setup Hold SCK to out SCK to SS high SS high to tri-state SS low to SCK Mode Master Master Master Master Master Master Master Master Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave 2 * tck 20 10 10 tck 15 4 * tck 2 * tck 1.6 Min. Typ. See Table 14-5 50% duty cycle 3.6 10 10 0.5 * tsck 10 10 15 ns Max.
In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12 MHz - 3 tCLCL for fCK >12 MHz
Figure 22-3.
SPI Interface Timing Requirements (Master Mode)
SS
6 1
SCK (CPOL = 0)
2 2
SCK (CPOL = 1)
4 5 3
MISO (Data Input)
MSB 7
...
LSB 8
MOSI (Data Output)
MSB
...
LSB
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Figure 22-4.
SPI Interface Timing Requirements (Slave Mode)
SS
9 10 16
SCK (CPOL = 0)
11 11
SCK (CPOL = 1)
13 14 12
MOSI (Data Input)
MSB 15
...
LSB 17
MISO (Data Output)
MSB
...
LSB
X
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22.7 ADC Characteristics
ADC Characteristics - TA = -45C to +105C, VCC = 2.7V to 5.5V (unless otherwise noted)
Parameter Condition Single Ended Conversion Resolution Differential conversion, Gain=5X or 10x Differential conversion, Gain=20X or 40x Single Ended Conversion Vcc=4V,VREF = 4V ADC clock = 1 MHz Single Ended Conversion Vcc=2.7V,VREF =2.56V ADC clock = 2 MHz Absolute accuracy Differential conversion, Gain=5X or 10x Vcc=5V,VREF = 4V ADC clock = 1 MHz Differential conversion, Gain=20X or 40x Vcc=5V,VREF = 4V ADC clock = 2MHz Single Ended Conversion Vcc=4V,VREF = 4V ADC clock = 1 MHz Single Ended Conversion Vcc=4V,VREF = 4V ADC clock = 2 MHz Single Ended Conversion Vcc=2.7V,VREF =2.56V ADC clock = 2 MHz Differential conversion, Gain=5X or 10x Vcc=5V,VREF = 4V ADC clock = 1 MHz Differential conversion, Gain=20X or 40x Vcc=5V,VREF = 4V ADC clock = 2MHz Min Typ 10 8 8 Bits Max Units
Table 22-6.
Symbol
2
4
2.2
4
LSB 1.2 2.0
1.5
3.0
0.6
1
0.8
1.5
1.0
2.5 LSB
Integral Non-linearity
0.5
1.0
0.8
2.0
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Table 22-6.
Symbol
ADC Characteristics - TA = -45C to +105C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)
Parameter Condition Single Ended Conversion Vcc=4V,VREF = 4V ADC clock = 1 MHz Single Ended Conversion Vcc=4V,VREF = 4V ADC clock = 2 MHz Single Ended Conversion Vcc=2.7V,VREF =2.56V ADC clock = 2 MHz Differential conversion, Gain=5X or 10x Vcc=5V,VREF = 4V ADC clock = 1 MHz Differential conversion, Gain=20X or 40x Vcc=5V,VREF = 4V ADC clock = 2MHz Single Ended Conversion Vcc=4V,VREF = 4V ADC clock = 1 MHz Gain Error Single Ended Conversion Vcc=2.7V,VREF =2.56V ADC clock = 2 MHz Differential conversion, Vcc=5V,VREF = 4V ADC clock = 1 MHz Single Ended Conversion Vcc=4V,VREF = 4V ADC clock = 1 MHz Offset Error Single Ended Conversion Vcc=2.7V,VREF =2.56V ADC clock = 2 MHz Differential conversion, Vcc=5V,VREF = 4V ADC clock = 1 MHz Conversion Time Clock Frequency Single Conversion 0.0 Min Typ 0.2 Max 0.5 Units
0.6
1
1.0
2.5 LSB
Differential Non-linearity
0.3
0.8
0.5
1.0
-6.0
0.0
-6.0
LSB
-2.0
+2.0
-1.0
2.0
1.0
4.0
LSB
-1.0 8 50 VCC - 0.3 2.56
+1.0 260 2000 VCC + 0.3 AVCC - 0.6 VREF +VREF/Gain 38.5 4 kHz kHz s kHz V V
AVCC VREF VIN
Analog Supply Voltage Reference Voltage Single Ended Conversion Input voltage Differential Conversion Single Ended Conversion Input bandwidth Differential Conversion
GND -VREF/Gain
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Table 22-6.
Symbol RREF RAIN CAIN IHSM
ADC Characteristics - TA = -45C to +105C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)
Parameter Reference Input Resistance Analog Input Resistance Analog Input Capacitor Increased Current Consumption High Speed Mode Single Ended Conversion Condition Min Typ 30 23 10 380 Max Units k K pF A
22.8
DAC Characteristics
DAC Characteristics - TA = -45C to +105C, VCC = 2.7V to 5.5V (unless otherwise noted)
Parameter Resolution Absolute accuracy Integral Non-linearity Differential Non-linearity Gain Error Offset Error Condition DAC Vcc=4V,VREF = 4V Vcc=4V,VREF = 4V Vcc=4V,VREF = 4V Vcc=4V,VREF = 4V Vcc=4V,VREF = 4V -5.0 0.0 2.56 Min Typ 10 2.5 0.8 0.2 5 1.5 0.5 0.0 2.0 AVCC LSB LSB LSB LSB LSB V Max Units
Table 22-7.
Symbol
VREF
Reference Voltage
22.9
Parallel Programming Characteristics
Figure 22-5. Parallel Programming Timing, Including some General Timing Requirements
tXLWL XTAL1 tDVXH tXHXL tXLDX
Data & Contol (DATA, XA0, XA1/BS2, PAGEL/BS1) tBVPH tPLBX t BVWL tWLWH WR RDY/BSY tWLRH tPLWL
WLRL
tWLBX
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Figure 22-6.
LOAD ADDRESS (LOW BYTE)
Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD DATA (LOW BYTE)
t XLXH
LOAD DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
XTAL1
PAGEL/BS1
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1/BS2
Note:
1. The timing requirements shown in Figure 22-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.
Figure 22-7.
Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)
READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE)
LOAD ADDRESS (LOW BYTE)
tXLOL
XTAL1
tBVDV
PAGEL/BS1
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1/BS2
Note:
1. The timing requirements shown in Figure 22-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
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Table 22-8.
Symbol VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tXLPH tPLXH tBVPH tPHPL tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL tBVDV tOLDV tOHDZ Notes: 1. 2.
Parallel Programming Characteristics, VCC = 5V 10%
Parameter Programming Enable Voltage Programming Enable Current Data and Control Valid before XTAL1 High XTAL1 Low to XTAL1 High XTAL1 Pulse Width High Data and Control Hold after XTAL1 Low XTAL1 Low to WR Low XTAL1 Low to PAGEL high PAGEL low to XTAL1 high BS1 Valid before PAGEL High PAGEL Pulse Width High BS1 Hold after PAGEL Low BS2/1 Hold after WR Low PAGEL Low to WR Low BS1 Valid to WR Low WR Pulse Width Low WR Low to RDY/BSY Low WR Low to RDY/BSY High
(1) (2)
Min. 11.5
Typ.
Max. 12.5 250
Units V A ns ns ns ns ns ns ns ns ns ns ns ns ns ns
67 200 150 67 0 0 150 67 150 67 67 67 67 150 0 3.7 7.5 0 0 250 250 250 1 5 10
s ms ms ns ns ns ns
WR Low to RDY/BSY High for Chip Erase XTAL1 Low to OE Low BS1 Valid to DATA valid OE Low to DATA Valid OE High to DATA Tri-stated
tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. tWLRH_CE is valid for the Chip Erase command.
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23. AT90PWM81 Typical Characteristics
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.
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23.1 Active Supply Current
Figure 23-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
1.2
5.5V
1
5V
0.8 ICC [mA]
4.5V 4V
0.6
3.6V 3.3V 2.7V
0.4
0.2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz]
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Figure 23-2.
Active Supply Current vs. Frequency (1 - 16 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
14 12 10 8 6 4 2 0 1 3 5 7 9 Frequency [MHz] 11 13 15
5.5V 5V 4.5V
ICC [mA]
4V 3.6V 3.3V 2.7V
Figure 23-3.
Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz 10 9 8 7 6 ICC [mA] 5 4 3 2 1 0 2.7 3.2 3.7 4.2 V CC [V] 4.7 5.2
T
L E MP CT E A T AR H EC OB
E AT
IZE R
D
125C 105C 25C -40C
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Figure 23-4. Active Supply Current vs. VCC (External clock, 16 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
EXTERNAL CLOCK 16 MHz - ATD ON 16 14 12 10 ICC [mA] 8 6 4 2 0 2.7 3.2 3.7 4.2 V CC [V] 4.7 5.2
125C 105C 25C -40C
23.2
Idle Supply Current
Figure 23-5. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. LOW FREQUENCY
0.35
5.5V
0.3
5V
0.25 0.2 0.15 0.1 0.05 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz]
4.5V 4V 3.6V 3.3V 2.7V
ICC [mA]
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Figure 23-6.
Idle Supply Current vs. Frequency (1 - 16 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
5 4.5
5.5V 5V
4 3.5 3 ICC [mA] 2.5 2 1.5 1 0.5 0 1 3 5 7 9 Frequency [MHz] 11 13 15
4.5V 4V 3.6V 3.3V 2.7V
Figure 23-7.
Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
4 3.5 3 2.5 ICC [mA] 2 1.5 1 0.5 0 2.7 3.2 3.7 4.2 V CC [V] 4.7 5.2
125C 105C 25C -40C
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Figure 23-8. Idle Supply Current vs. VCC (External clock, 16 MHz)
IDLE SUPPLY CURRENT vs. VCC
EXTERNAL CLOCK 16 MHz 6 -40C 125C 105C 25C
5
4 ICC [mA]
3
2
1
0 2.7 3.2 3.7 4.2 V CC [V] 4.7 5.2
23.3
Power-Down Supply Current
Figure 23-9. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED 12
10
125C
8 ICC [uA]
6
4
105C
2
25C
0 2.7 3.2 3.7 4.2 V CC [V] 4.7 5.2
-40C
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Figure 23-10. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED 25
20
125C
15 ICC [uA]
10
105C -40C 25C
5
0 2.7 3.2 3.7 4.2 V CC [V] 4.7 5.2
23.4
Pin Pull-up
Figure 23-11. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5V 160
105C 140 -40C
120 100 IOP [uA] 80 60 40 20 0 0
25C
125C
E IZE AT L ER MP CT A TE AR H EC OB T
D
0.5
1
1.5
2
2.5 V OP [V]
3
3.5
4
4.5
5
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Figure 23-12. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V 80
-40C
70 60 50 IOP [uA] 40 30 20 10 0 0
25C
105C 125C
0.5
1
1.5
2
2.5 V OP [V]
3
3.5
4
4.5
5
Figure 23-13. I/O Pin Pull-Up Resistor Current vs. Input Voltage, PE1 & PE2 pins (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
PE1 & PE2 PINS 160 Vcc = 5V
105C -40C
140 120 100 IOP [uA] 80 60 40 20 0 0
25C
125C
0.5
1
1.5
2
2.5 V OP [V]
3
3.5
4
4.5
5
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Figure 23-14. I/O Pin Pull-Up Resistor Current vs. Input Voltage, PE1 & PE2 pins (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
PE1 & PE2 PINS 90 Vcc = 2.7V
-40C 105C
80 70 60
25C
125C
IOP [uA]
50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 V OP [V] 3 3.5 4 4.5 5
Figure 23-15. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 5V 120
-40C 105C
100
25C
125C
80 IRESET [uA]
60
40
20
0 0 0.5 1 1.5 2 2.5 V RESET [V] 3 3.5 4 4.5 5
288
AT90PWM81
7734P-AVR-08/10
AT90PWM81
Figure 23-16. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 2.7V 60
-40C 105C
50
25C
125C
40 IRESET [uA]
30
20
10
0 0 0.5 1 1.5 2 2.5 V RESET [V] 3 3.5 4 4.5 5
23.5
Pin output high voltage
Figure 23-17. I/O Pin Output Voltage vs. Source current (Vcc = 5V))
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
Vcc = 5.0 V 6
5
-40C 125C 25C 105C
4 V OH [V]
3
2
1
0 0 1 2 3 4 5 IOH [mA] 6 7 8 9 10
289
7734P-AVR-08/10
Figure 23-18. I/O Pin Output Voltage vs. Source current (Vcc = 3V))
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
Vcc = 3.0 V 3.5 3 2.5 2
-40C 25C 105C 125C
V OH [V]
1.5 1 0.5 0 0 1 2 3 4 5 IOH [mA] 6 7 8 9 10
23.6
Pin output low voltage
Figure 23-19. I/O Pin Output Voltage vs. Sink current (Vcc = 5V))
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
Vcc = 5.0 V 0.6
0.5
125C 105C 25C
0.4 V OL [V]
0.3
-40C
0.2
0.1
0 0 1 2 3 4 5 IOL [mA] 6 7 8 9 10
290
AT90PWM81
7734P-AVR-08/10
AT90PWM81
Figure 23-20. I/O Pin Output Voltage vs. Sink current (Vcc = 3V))
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
Vcc = 3.0 V 0.8 0.7 0.6 0.5 V OL [V] 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 IOL [mA] 6 7 8 9 10
125C 105C
25C -40C
23.7
Pin Thresholds
Figure 23-21. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0')
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0' 3
125C
2.5
105C 25C
-40C
2 Threshold [V]
1.5
1
0.5
0 2.7 3.2 3.7 4.2 V CC [V] 4.7 5.2
291
7734P-AVR-08/10
Figure 23-22. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read As '1')
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1' 4 3.5 3 2.5 2 1.5 1 0.5 0 2.7 3.2 3.7 4.2 V CC [V] 4.7 5.2
125C 105C -40C 25C
23.8
BOD Thresholds
Figure 23-23. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL is 4.3V 4.6 4.5 4.4
Threshold [V]
Rising Vcc
Falling Vcc
Threshold [V] 4.3 4.2 4.1 4 3.9 3.8 -40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100 110 120
Temperature [C]
292
AT90PWM81
7734P-AVR-08/10
AT90PWM81
Figure 23-24. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL is 2.7V 2.9
Rising Vcc
2.8
Threshold [V]
2.7
Falling Vcc
2.6
2.5
2.4 -40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100 110 120
Temperature [C]
23.9
Analog Reference
Figure 23-25. VREF Voltage vs. VCC
IINTERNAL VREF vs Vcc
2.65 2.6 2.55 2.5 2.45 2.4 2.35 2.3 2.7 3.2 3.7 4.2 Vcc (V) 4.7 5.2
125C 105C 25C
VRef (V)
-40C
293
7734P-AVR-08/10
Figure 23-26. VREF Voltage vs. Temperature
INTERNAL VREF vs TEMPERATURE
2.65
5.5V
2.6
2.7V
2.55 Aref (V)
2.5
2.45
2.4
2.35 -40 -30 -20 -10
0
10
20
30 40 50 60 Temperature (C)
70
80
90
100 110 120
23.10 Internal Oscillator Speed
Figure 23-27. Watchdog Oscillator Frequency vs. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE
0.14 0.135 0.13
-40C
0.125 FRC [MHz] 0.12
25C
125C
0.115 0.11 0.105 0.1 2.7 3.2 3.7 4.2 V CC [V] 4.7 5.2
105C
294
AT90PWM81
7734P-AVR-08/10
AT90PWM81
Figure 23-28. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
RC OSC CALIBRATED @ ROOM TEMP 8.3
8.2
5.6V 5.4V 5.2V 5V4V 2.6V 2.8V
8.1 FRC [MHz]
8
V
7.9
7.8
7.7 -40
-25
-10
5
20
35 50 Temperature
65
80
95
110
125
Figure 23-29. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE
RC OSC CALIBRATED @ ROOM TEMP 8.3 8.2 8.1 FRC [MHz] 8 7.9 7.8 7.7 7.6 2.4 2.9 3.4 3.9 V CC [V] 4.4 4.9 5.4
125C 105C
25C
-40C
295
7734P-AVR-08/10
Figure 23-30. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value
INT RC OSCILLATOR Frequency vs. OSCCAL
10000 Cycles sampled w ith 250nS - VCC 3 V
105C
1600000
25C
-40C
1400000
1200000 FRC
1000000
800000
600000
400000 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL
23.11 Current Consumption in Reset
Figure 23-31. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pullup)
RESET SUPPLY CURRENT vs Vcc
EXCLUDING CURRENT THROUGH THE RESET PULLUP 1 0.9 0.8 0.7 ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency MHz All temperatures
5.5V
2.7V
296
AT90PWM81
7734P-AVR-08/10
AT90PWM81
Figure 23-32. Reset Supply Current vs. VCC (1 - 16 MHz, Excluding Current through the Reset Pull-up)
RESET SUPPLY CURRENT vs VCC
EXCLUDING CURRENT THROUGH THE RESET PULLUP 4 3.5 3 2.5 ICC (mA) 2
5.5V
1.5 1 0.5 0 1 3 5 7 9 Frequency MHz All temperatures 11 13 15
2.7V
297
7734P-AVR-08/10
24. Register Summary
Address
(0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0)
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit 7
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Bit 6
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Bit 5
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Bit 4
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Bit 3
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Bit 2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Bit 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Bit 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Page
298
AT90PWM81
7734P-AVR-08/10
AT90PWM81
Address
(0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x9r) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E)
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ICR1H ICR1L Reserved TCCR1B EICRA OSCCAL PLLCSR PRR CLKSELR CLKCSR CLKPR WDTCSR BGCCR BGCRR AC3CON AC2CON
Bit 7
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICR115 ICR17 - ICNC1 - - PRPSC2 -
Bit 6
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICR114 ICR16 - ICES1 - CAL6 -
Bit 5
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICR113 ICR15 - - ISC21 CAL5 PLLF3 PRPSCR
Bit 4
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICR112 ICR14 - WGM13 ISC20 CAL4 PLLF2 PRTIM1
Bit 3
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICR111 ICR13 - - ISC11 CAL3 PLLF1 -
Bit 2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICR110 ICR12 - CS12 ISC10 CAL2 PLLF0 PRSPI
Bit 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICR19 ICR11 - CS11 ISC01 CAL1 PLLE -
Bit 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICR18 ICR10 - CS10 ISC00 CAL0 PLOCK PRADC
Page
page 97 page 97 page 96 page 82 page 38 page 40 page 47 page 42 page 41 page 41 page 46 page 191 page 191 page 199 page 199
COUT
- - WDIE - - AC3IE AC2IE
CSUT1
- - WDP3 - - AC3IS1 AC2IS1
CLKCCE
CLKPCE WDIF - AC3EN AC2EN
CSUT0 CLKRDY
- WDCE - - AC3IS0 AC2IS0
CSEL3 CLKC3
CLKPS3 WDE
CSEL2 CLKC2
CLKPS2 WDP2
CSEL1 CLKC1
CLKPS1 WDP1
CSEL0 CLKC0
CLKPS0 WDP0
BGCC3 BGCR3
AC3OEA -
BGCC2 BGCR2
AC3M2 AC2M2
BGCC1 BGCR1
AC3M1 AC2M1
BGCC0 BGCR0
AC3M0 AC2M0
299
7734P-AVR-08/10
Address
(0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C)
Name
AC1CON AC3ECON AC2ECON AC1ECON AMP0CSR DIDR1 DIDR0 DACON
Bit 7
AC1EN - - - AMP0EN -
ADC8D/AMP3D
Bit 6
AC1IE - - - AMP0IS -
ADC7D/AMP0-D
Bit 5
AC1IS1 AC3OI AC2OI AC1OI AMP0G1 -
ADC5D/ACMP2D
Bit 4
AC1IS0 AC3OE AC2OE AC1OE AMP0G0 -
ADC4D/ACMP3M
Bit 3
- - - AC1ICE AMP0GS
ACMP1MD ADC3D/ACMPMD
Bit 2
AC1M2 AC3H2 AC2H2 AC1H2 -
AMP0+D ADC2D/ACMP2M
Bit 1
AC1M1 AC3H1 AC2H1 AC1H1 AMP0TS1
ADC10D ADC1D
Bit 0
AC1M0 AC3H0 AC2H0 AC1H0 AMP0TS0
ADC9D ADC0D/ACMP1D
Page
page 197 page 197 page 197 page 197 page 224 page 221 page 221 page 228
DAATE
DATS2
DATS1
DATS0
-
DALA
-
DAEN
Room for analog test registers
PASDLY2 PCNFE2 POM2 PSOC2 PICR2H PICR2L Reserved PSOC0 PICR0H PICR0L PFRC2B PFRC2A OCR2SAH OCR2SAL PFRC0B PFRC0A OCR0SAH OCR0SAL SREG SPH SPL Reserved TCNT1H TCNT1L DACH DACL SPMCSR SPDR MCUCR MCUSR SMCR MSMCR DWDR Reserved OCR2RAH OCR2RAL ADCH ADCL OCR0RAH OCR0RAL OCR2RBH OCR2RBL OCR2SBH OCR2SBL OCR0RBH OCR0RBL OCR0SBH OCR0SBL EIMSK EIFR EEARH EEARL EEDR EECR - - - EEAR7 EEDR7 NVMBSY - - - EEAR6 EEDR6 EEPAGE - - - EEAR5 EEDR5 EEPM1 - - - - - - - OCR0RB[15:12] - - - - OCR2RB[15:12] - / ADC9 ADC7 / ADC1 - - / ADC8 ADC6 / ADC0 - - / ADC7 ADC5 / - - - - - - - - - I - SP7 - TCNT115 TCNT17 - / DAC9 DAC7 / DAC1 SPMIE SPD7 - - - T - SP6 - TCNT114 TCNT16 - / DAC8 DAC6 /DAC0 RWWSB SPD6 - - - H - SP5 - TCNT113 TCNT15 - / DAC7 DAC5 / SIGRD SPD5 - - - S - SP4 - PCAE0B PCAE0A - PISEL0B PISEL0A - PELEV0B PELEV0A - PCAE2B PCAE2A - PISEL2B PISEL2A - PELEV2B PELEV2A - - PISEL0A1 PCST0 - PISEL0B1 - - PSYNC01 - -
PASDLY2[7:0]
page 135
PASDLKn2
POMV2B3 POS23 PCST2
PASDLKn1
POMV2B2 POS22 -
PASDLKn0
POMV2B1 PSYNC21 -
PBFMn1
POMV2B0 PSYNC20 -
PELEVnA1
POMV2A3 POEN2D
PELEVnB1
POMV2A2 POEN2B
PISEL0A1
POMV2A1 POEN2C
PISEL0B1
POMV2A0 POEN2A
page 135 page 142 page 133 page 142 page 142
PICR2[11:8] PICR2[7:0] - - - POEN0B PICR0[11:8] PICR0[7:0] PRFM2B3 PRFM2A3 PRFM2B2 PRFM2A2 PRFM2B1 PRFM2A1 PRFM2B0 PRFM2A0 - - - POEN0A
PSYNC00 - PFLTE2B PFLTE2A - OCR2SA[7:0] PFLTE0B PFLTE0A - OCR0SA[7:0]
page 171 page 177 page 177 page 140 page 140 page 134 page 134
OCR2SA[11:8] PRFM0B3 PRFM0A3 PRFM0B2 PRFM0A2 PRFM0B1 PRFM0A1 PRFM0B0 PRFM0A0
page 175 page 175 page 172 page 172
OCR0SA[11:8] V SP11 SP3 - TCNT111 TCNT13 - / DAC5 DAC3 / BLBSET SPD3 RSTDIS WDRF SM2 DWDR[7:0] - OCR2RA[7:0] - - OCR2RA[11:8] - / ADC5 ADC3 / - / ADC4 ADC2 / ADC9 / ADC3 ADC1 / ADC8 / ADC2 ADC0 / - N SP10 SP2 - TCNT110 TCNT12 - / DAC4 DAC2 / PGWRT SPD2 CKRC81 BORF SM1 Z SP9 SP1 - TCNT19 TCNT11 DAC9 / DAC3 DAC1 / PGERS SPD1 IVSEL EXTRF SM0 C SP8 SP0 - TCNT18 TCNT10 DAC8 / DAC2 DAC0 / SPMEN SPD0 IVCE PORF SE
page 9 page 12 page 12 page 97 page 97 page 229 page 229 page 238 page 188 page 54 & page 72 page 53 page 47 reserved page 232 page 134 page 134 page 220 page 220 page 172 page 172 page 135 page 135 page 135 page 135 page 173 page 173 page 172 page 172
TCNT112 TCNT14 - / DAC6 DAC4 / RWWSRE SPD4 PUD - -
Monitor Stop Mode Control Register
- / ADC6 ADC4 / -
OCR0RA[11:8] OCR0RA[7:0] OCR2RB[11:8] OCR2RB[7:0] OCR2SB[11:8] OCR2SB[7:0] OCR0RB[11:8] OCR0RB[7:0] OCR0SB[11:8] OCR0SB[7:0] - - - EEAR3 EEDR3 EERIE INT2 INTF2 - EEAR2 EEDR2 EEMWE INT1 INTF1 - EEAR1 EEDR1 EEWE INT0 INTF0 EEAR8 EEAR0 EEDR0 EERE
page 83 page 83 page 19 page 19 page 19 page 19
EEAR4 EEDR4 EEPM0
300
AT90PWM81
7734P-AVR-08/10
AT90PWM81
Address
0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
GPIOR2 GPIOR1 GPIOR0 SPSR SPCR PCTL2 PCNF2 PIFR2 PIM2 PCTL0 PCNF0 PIFR0 PIM0 PORTE DDRE PINE PORTD DDRD PIND ADMUX ADCSRB ADCSRA PORTB DDRB PINB TIFR1 TIMSK1 ACSR
Bit 7
GPIOR27 GPIOR17 GPIOR07 SPIF SPIE PPRE21 PFIFTY2 POAC2B PPRE01 PFIFTY0 POAC0B - - - PORTD7 DDD7 PIND7 REFS1 ADHSM ADEN PORTB7 DDB7 PINB7 - - AC3IF
Bit 6
GPIOR26 GPIOR16 GPIOR06 WCOL SPE PPRE20 PALOCK2 POAC2A PPRE00 PALOCK0 POAC0A - - - PORTD6 DDD6 PIND6 REFS0 ADNCDIS ADSC PORTB6 DDB6 PINB6 - - AC2IF
Bit 5
GPIOR25 GPIOR15 GPIOR05 - DORD PBFM2 PLOCK2 PSEI2 PSEIE2 PBFM01 PLOCK0 - - - - - PORTD5 DDD5 PIND5 ADLAR - ADATE PORTB5 DDB5 PINB5 ICF1 ICIE1 AC1IF
Bit 4
GPIOR24 GPIOR14 GPIOR04 - MSTR PAOC2B PMODE21 PEV2B PEVE2B PAOC0B PMODE01 PEV0B PEVE0B - - - PORTD4 DDD4 PIND4 - ADSSEN ADIF PORTB4 DDB4 PINB4 - - -
Bit 3
GPIOR23 GPIOR13 GPIOR03 - CPOL PAOC2A PMODE20 PEV2A PEVE2A PAOC0A PMODE00 PEV0A PEVE0A - - - PORTD3 DDD3 PIND3 MUX3 ADTS3 ADIE PORTB3 DDB3 PINB3 - - AC3O
Bit 2
GPIOR22 GPIOR12 GPIOR02 - CPHA PARUN2 POP2 PRN21 PBFM00 POP0 PRN01 - PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 MUX2 ADTS2 ADPS2 PORTB2 DDB2 PINB2 - - AC2O
Bit 1
GPIOR21 GPIOR11 GPIOR01 - SPR1 PCCYC2 PCLKSEL2 PRN20 PEOEPE2 PCCYC0 PCLKSEL0 PRN00 PEOEPE0 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 MUX1 ADTS1 ADPS1 PORTB1 DDB1 PINB1 - - AC1O
Bit 0
GPIOR20 GPIOR10 GPIOR00 SPI2X SPR0 PRUN2 POME2 PEOP2 PEOPE2 PRUN0 - PEOP0 PEOPE0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 MUX0 ADTS0 ADPS0 PORTB0 DDB0 PINB0 TOV1 TOIE1 -
Page
page 26 page 26 page 26 page 188 page 186 page 139 page 135 page 144 page 143 page 174 page 173 page 178 page 178 page 80 page 81 page 81 page 80 page 80 page 80 page 216 page 219 page 218 page 80 page 80 page 80 page 98 page 97 page 201
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM81 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
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25. Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k
Description
Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled
Operation
Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS
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Mnemonics
SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr
Operands
P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
Description
Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
Operation
I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK
Flags
None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2
BIT AND BIT-TEST INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack MCU CONTROL INSTRUCTIONS
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Mnemonics
NOP SLEEP WDR BREAK
Operands
Description
No Operation Sleep Watchdog Reset Break
Operation
(see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only
Flags
None None None None
#Clocks
1 1 1 N/A
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26. Ordering Information
Speed (MHz) 16 16 16 16 16 16 Note: Note: Note: Note: Note: Power Supply 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V Ordering Code AT90PWM81-16ME AT90PWM81-16SE AT90PWM81-16MN AT90PWM81-16SN AT90PWM81-16MF AT90PWM81-16SF Package QFN32 SO20 QFN32 SO20 QFN32 SO20
(3) (2) (1)
Operation Range Engineering Samples Engineering Samples Extended (-40C to 105C) Extended (-40C to 105C) Extended (-40C to 125C) Extended (-40C to 125C)
All packages are Pb free, fully LHF This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Parts numbers are for shipping in sticks (SO) or in trays (QFN). Thes devices can also be supplied in Tape and Reel. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. P/N for Extended -40C to 125C are not yet defined 1. Marking on the package is PWM81-ME. 2. Marking on the package is PWM81-MN. 3. Marking on the package is PWM81-MF.
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27. Package Information
Package Type TG, 20-Lead, 0.300" Body Width Plastic Gull Wing Small Outline Package (SOIC) PN, 32-Lead, 5.0 x 5.0 mm Body, 0.50mm Pitch Quad Flat No lead Package (QFN)
SO20
QFN32
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27.1 SO20
307
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27.2
QFN32
308
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28. Errata
28.1
Errata AT90PWM81 revA
* Available on request
28.2
Errata AT90PWM81 revB
* * * * * * * * Clock Switch disable Crystal oscillator control with Clock Switch BOD disable fuse PSC output at Reset Flash and EEPROM programming failure if CPU clock is switched ADC AMPlifier measurement is unstable ADC measurement reports abnormal values with PSC2-synchronized conversions Over-consumption in power down sleep mode 1. Clock Switch enable & disable After a "Enable Clock Source" or a "Disable Clock Source" command, the command is still active until the next access of CLKCSR register. If CLKSEL is written with a new value, the corresponding clock will be unintentionnaly enabled or disabled. Work around: After the Enable or Disable command, write CLKCSR with value 1<309
7734P-AVR-08/10
5. Flash and EEPROM programming failure if CPU clock is switched If Clock switching is used in the Application, the memory programming is only possible when the internal RC oscillator is selected as System clock. If the Application requires a memory programming on a clock source different from the internal RC oscillator, do not switch to this clock source. Work around: - Use internal RC oscillator when programming Flash and EEPROM, or - Do not use clock switching. 6. ADC AMPlifier measurement is unstable When switching from a single-ended ADC channel to an Amplified channel, noise can appear on ADC conversion. Work around: After switching from a single ended to an amplified channel, discard the first ADC conversion. 7. ADC measurement reports abnormal values with PSC2-synchronized conversions When using ADC in synchronized mode, an unexpected extra Single ended conversion can spuriously re-start.This can occur when the End of conversion and the Trigger event occur at the same time. Work around: No workaround 8. Over-consumption in power down sleep mode. In Power-down mode, an extra power consumption up to 500A may occur. Work around: No workaround
28.3
Errata AT90PWM81 revC
* * * * * * * * Clock Switch disable Crystal oscillator control with Clock Switch BOD disable fuse PSC output at Reset Flash and EEPROM programming failure if CPU clock is switched ADC AMPlifier measurement is unstable ADC measurement reports abnormal values with PSC2-synchronized conversions Over-consumption in power down sleep mode.
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1. Clock Switch enable & disable After a "Enable Clock Source" or a "Disable Clock Source" command, the command is still active until the next access of CLKCSR register. If CLKSEL is written with a new value, the corresponding clock will be unintentionnaly enabled or disabled. Work around: Atter the Enable or Disable command, write CLKCSR with value 1<2. Crystal oscillator control with Clock Switch When a Xtal oscillator is active and CLKSELR is written with a new value for the selection of another clock source (for instance RC or WD) , the Xtal oscillator gain is not correct. Work around: After the commands "Enable Clock Source" and "Clock Source Switching", write back CLKSELR with the values corresponding to the active Xtal oscillator 3. BOD disable fuse It is strongly advised to keep the BOD active. Indeed, the RC oscillator may lock if it is activated when the power suppy goes at a low voltage. Work around: If it is mandatory to disable the BOD, do not set the RC oscillator as clock source during reset and makes sure the RC oscillator is never active when the power supply is below the lowest POR voltage (2.6V). 4. PSC output at Reset At Reset, the PSC outputs may be set at a value different from the PSC Fuse configuration (Bit 4 of Extended Fuse Byte). Work around: Initiate PSC output states from source code. 5. Flash and EEPROM programming failure if CPU clock is switched If Clock switching is used in the Application, the memory programming is only possible when the internal RC oscillator is selected as System clock. If the Application requires a memory programming on a clock source different from the internal RC oscillator, do not switch to this clock source. Work around: - Use internal RC oscillator when programming Flash and EEPROM, or - Do not use clock switching 6. ADC AMPlifier measurement is unstable When switching from a single-ended ADC channel to an Amplified channel, noise can appear on ADC conversion. Work around: After switching from a single ended to an amplified channel, discard the first ADC conversion.
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7. ADC measurement reports abnormal values with PSC2-synchronized conversions When using ADC in synchronized mode, an unexpected extra Single ended conversion can spuriously re-start.This can occur when the End of conversion and the Trigger event occur at the same time. Work around: No workaround 8. Over-consumption in power down sleep mode. In Power-down mode, an extra power consumption up to 500A may occur. Work around: No workaround
28.4
Errata AT90PWM81 revD
* * * * * * * Clock Switch disable Crystal oscillator control with Clock Switch BOD disable fuse Flash and EEPROM programming failure if CPU clock is switched ADC Amplifier measurement is unstable ADC measurement reports abnormal values with PSC2-synchronized conversions Over-consumption in power down sleep mode 1. Clock Switch enable & disable After a "Enable Clock Source" or a "Disable Clock Source" command, the command is still active until the next access of CLKCSR register. If CLKSEL is written with a new value, the corresponding clock will be unintentionnaly enabled or disabled. Work around: Atter the Enable or Disable command, write CLKCSR with value 1<312
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4. Flash and EEPROM programming failure if CPU clock is switched If Clock switching is used in the Application, the memory programming is only possible when the internal RC oscillator is selected as System clock. If the Application requires a memory programming on a clock source different from the internal RC oscillator, do not switch to this clock source. Work around: - Use internal RC oscillator when programming Flash and EEPROM, or - Do not use clock switching 5. ADC AMPlifier measurement is unstable When switching from a single-ended ADC channel to an Amplified channel, noise can appear on ADC conversion. Work around: After switching from a single ended to an amplified channel, discard the first ADC conversion. 6. ADC measurement reports abnormal values with PSC2-synchronized conversions When using ADC in synchronized mode, an unexpected extra Single ended conversion can spuriously re-start.This can occur when the End of conversion and the Trigger event occur at the same time. Work around: No workaround 7. Over-consumption in power down sleep mode. In Power-down mode, an extra power consumption up to 500A may occur. Work around: No workaround
28.5
Errata AT90PWM81 revE
* * * Clock Switch disable Crystal oscillator control with Clock Switch BOD disable fuse 1. Clock Switch enable & disable After a "Enable Clock Source" or a "Disable Clock Source" command, the command is still active until the next access of CLKCSR register. If CLKSEL is written with a new value, the corresponding clock will be unintentionnaly enabled or disabled. Work around: Atter the Enable or Disable command, write CLKCSR with value 1<313
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2. Crystal oscillator control with Clock Switch When a Xtal oscillator is active and CLKSELR is written with a new value for the selection of another clock source (for instance RC or WD) , the Xtal oscillator gain is not correct. Work around: After the commands "Enable Clock Source" and "Clock Source Switching", write back CLKSELR with the values corresponding to the active Xtal oscillator 3. BOD disable fuse It is strongly advised to keep the BOD active. Indeed, the RC oscillator may lock if it is activated when the power suppy goes at a low voltage. Work around: If it is mandatory to disable the BOD, do not set the RC oscillator as clock source during reset and makes sure the RC oscillator is never active when the power-supply is below the lowest supply voltage (2.6V).
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29. Datasheet Revision History for AT90PWM81
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.
29.1
Rev. 7734A
1. Document creation.
29.2
Rev. 7734B
1. GPIO3 suppressed for compatibility reason 2. Pinout: PB7 & PD7 swapped 3. CKSEL values redefined 4. Clock switching & clock monitoring added 5. PSCrOUT name changed to PSCOUTR 6. ADC Auto trigger on PSC synchro improved. 7. Parallel programming updated for 20 pins 8. Fuses updated: compatibility & potential conflict for reset levels
29.3
Rev. 7734C
1. Pin out change request 2. Several improvements on paragraph indent and numbering 3. P28-29: Device clock option select 4. P194: BGD bit suppressed 5. P311-314: Register address changed
29.4
Rev. 7734D
1. Pin name AGND 2. PSC reduced support enhanced resolution (Application request)
29.5
Rev. 7734E
1. Speed at 3V, 12 Mhz 2. Add chapter Pin description (PE request) 3. Table 7-1 : PE function for 128k RC oscillator is I/O 4. Details on RC oscillator enable page 30 5. New warnings on clock switching page 40 6. Details on CKRC81 page 45 7. Wake up source PSC not available in PowedDown page 48 8. Typos on DIDR0/1 9. ADC sample & hold time on auto conversion 10. PSC input beheavior during reset precision 11. Update using the PRR examples with exsisting peripherals 12. Parallel programing input pins 13. I/O hysteresis curve
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29.6
Rev. 7734F
1. Clean chapter clock from all "Power save" 2. Update chapter "Calibrated Internal RC Oscillator" on page 29 3. Update Table 7-9 on page 35 : SUT for PLL 4. Update chapter Idle Mode page 48 5. Update figure "PSC Input Module A" on page 119 and "PSC Input Module B" on page 120 6. Update figure "PSC behavior versus PSCn Input B in Mode 14" on page 132 7. Update tables 14-16 "PSC edge & level input Selection" on page 142 & 14-17 "PSC edge & level input Selection" on page 142 8. Clean chaper PSC (no more PSC0 & PSC1 register) 9. PSCR registers and bits renamed from "r" to "0" 10. Update chapter "Digital Input Disable Register 0 - DIDR0" on page 207 & "Digital Input Disable Register 1- DIDR1" on page 208 11. Update figures on parallel programming :Figure 23-1 on page 261, Figure 23-3 on page 265,Figure 23-4 on page 266,Figure 23-5 on page 268 12. Suppress chapter "Parallel Programing Characteristic" after Section 23.7.14, now in "Parallel Programming Characteristics" on page 282
29.7
Rev. 7734G
1. Update pin out definitions with PE3 as AREF pin: Figures "20 Pin Packages" on page 4, "32Pin Packages" on page 5,Table "Pin out description" on page 7, Chapter "Port E (P32..0) RESET/ XTAL1/ XTAL2/AREF" on page 8 and Chapter "Alternate Functions of Port E" on page 82 2. Update Table 7-1 on page 28 , for CKSEL 0111, 1100 & 1101 3. Update figure "Analog to Digital Converter Block Schematic" on page 210 4. Update Table 19-3 on page 224; warning no more errata
29.8
Rev. 7734H
1. Udate Product configurationTable 2-1 on page 2 2. Add chapter "RC Oscillator calibration" on page 31 3. Update chapter "Internal Voltage Reference" on page 58 4. Update chapter "On Chip voltage Reference and Temperature sensor overview" on page 192 5. Update chapter "Temperature Measurement" on page 196 6. Update Figure "Analog Comparator Block Diagram" on page 201 7. Update chapter "Reading the Signature Row from Software" on page 250 8. Update chapter "Calibrated Internal RC Oscillator Accuracy" on page 277 9. Add chapter "Power consumption estimation with clock prescaling" on page 290 10. Update chapter "Errata" on page 325
29.9
Rev. 7734I
1. Remove PE3 I/O function (Only AREF and ADC functions) : Pages 3,4,6,7,80,81,223 2. Remove the `Enable Watchdog in Automatic Reload Mode' Page 34 and in Table 6-12 on Page 18 3. Update RC Calibartion section 6.2.2.1 page 30 4. Remove chapter 6.3.7 on Page 36 5. Remove chapter 16.3 Band Gap calibration procedure on Page 191 6. Update Temperature calibration on Page 191 7. Remove chapter 16.4.3 Two Points Temperature sensor calibration on Page 197
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8. Update Signature Row Addressing on Page249 9. Update DC Characteristics : Update table 23-1 Page 275 : RC calibartion @25C Update Table 23.2 page 272 : -40C in place of -45C New Table in 23.2 : -40C to +125C 10. Update Erratasheet
29.10 Rev. 7734J
1. Page 2 Table 2-1 : QFN32 : 32 Pins 2. Page 6 Table 3-2 : SO24 and QFN20 are removed 3. Page 30 section 6.2.2.1 : RC Osc. is monitored @125C 4. Page 51 : Table 8.2 : BODenable is mandatory 5. Page 166 : removed AT90PWM2/3 comments 6. Page 267 Table 23-1 : User Calibration at +5% 7. Page 271 Update of ADC Characteristics 8. Page 273 Add the DAC Characteristics
29.11 Rev. 7734K
1. Page 193 16.4.1 : removed the last sentence about reading of the temperature sensor during Hot testing 2. Page 193 16.4.1 : T formula modifed with new TSGAIN 3. Page 244 Table 21.5 : Signature row adressing table updated with right address
29.12 Rev. 7734L
1. Update Errata Rev E
29.13 Rev. 7734M
1. Page 204 : Figure 18-1 removed REFS2 bit 2. .Pages 277 to 294 : update of Typical characteristics
29.14 Rev. 7734N
1. Page 52 : update of BOD levels 2. .Pages 267,268,269,270 : update of Vref, Icc power-down, Icc operating, Icc Idle and Watchdog oscillator characteristics
29.15 Rev. 7734O
1. Pages 275,276 Table 23-6: update of ADC characteristics 2. .Page 270: add a new line in Table 23-1(Calibrated Internal RC oscillator Accuracy ) 3. .Pages 267, 269,279 : update of Analog comparator characteristics
29.16 Rev. 7734P
1. Updated "Electrical Characteristics(1)" on page 265 and "AT90PWM81 Typical Characteristics" on page 280
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Table Of Contents
1 2 Products Configuration ..........................................................................................2 Pin Configurations .................................................................................................3
2.1Pin Descriptions ....................................................................................................................... 6
3
AVR CPU Core .......................................................................................................8
3.1Introduction .............................................................................................................................. 8 3.2Architectural Overview ............................................................................................................ 8 3.3ALU - Arithmetic Logic Unit .................................................................................................. 9 3.4Status Register .......................................................................................................................... 9 3.5General Purpose Register File ................................................................................................ 11 3.6Stack Pointer .......................................................................................................................... 12 3.7Instruction Execution Timing ................................................................................................. 12 3.8Reset and Interrupt Handling ................................................................................................. 13
4
Memories ...............................................................................................................16
4.1In-System Reprogrammable Flash Program Memory ........................................................... 16 4.2SRAM Data Memory ............................................................................................................. 16 4.3EEPROM Data Memory ........................................................................................................ 18 4.4Fuse Bits ................................................................................................................................. 22 4.5I/O Memory ............................................................................................................................ 26 4.6General Purpose I/O Registers ............................................................................................... 26
5
System Clock and Clock Options .........................................................................27
5.1Clock Systems and their Distribution ..................................................................................... 27 5.2Clock Sources ......................................................................................................................... 28 5.3Dynamic Clock Switch ........................................................................................................... 35 5.4System Clock Prescaler .......................................................................................................... 38 5.5Register Description ............................................................................................................... 38
6
Power Management and Sleep Modes .................................................................44
6.1Sleep Modes ........................................................................................................................... 44 6.2Idle Mode ............................................................................................................................... 44 6.3ADC Noise Reduction Mode ................................................................................................. 45 6.4Power-down Mode ................................................................................................................. 45 6.5Standby Mode ........................................................................................................................ 45 6.6Power Reduction Register ...................................................................................................... 45 6.7Minimizing Power Consumption ........................................................................................... 45
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6.8Register description ................................................................................................................ 47
7
System Control and Reset .....................................................................................49
7.1System Control overview ....................................................................................................... 49 7.2System Control registers ........................................................................................................ 53 7.3Internal Voltage Reference ..................................................................................................... 54 7.4Watchdog Timer ..................................................................................................................... 55
8
Interrupts ..............................................................................................................61
8.1Interrupt Vectors in AT90PWM81 ........................................................................................ 61
9
I/O-Ports ................................................................................................................66
9.1Introduction ............................................................................................................................ 66 9.2Ports as General Digital I/O ................................................................................................... 67 9.3Alternate Port Functions ......................................................................................................... 71 9.4Register Description for I/O-Ports ......................................................................................... 80
10 11
External Interrupts ...............................................................................................82 Reduced 16-bit Timer/Counter1 ..........................................................................84
11.1Overview .............................................................................................................................. 84 11.2Accessing 16-bit Registers ................................................................................................... 86 11.3Timer/Counter Clock Sources .............................................................................................. 89 11.4Counter Unit ......................................................................................................................... 90 11.5Input Capture Unit ................................................................................................................ 91 11.6Modes of Operation .............................................................................................................. 93 11.7Timer/Counter Timing Diagrams ......................................................................................... 94 11.816-bit Timer/Counter Register Description .......................................................................... 95
12
Power Stage Controller - (PSCn) ........................................................................99
12.1Features ................................................................................................................................ 99 12.2Overview .............................................................................................................................. 99 12.3PSC Description ................................................................................................................. 100 12.4Signal Description .............................................................................................................. 102 12.5Functional Description ....................................................................................................... 104 12.6Update of Values ................................................................................................................ 109 12.7Enhanced Resolution .......................................................................................................... 110 12.8PSC Inputs .......................................................................................................................... 113 12.9PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait ......................... 120 12.10PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait ................................ 121
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12.11PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active .................. 122 12.12PSC Input Mode 4: Deactivate outputs without changing timing. ................................... 123 12.13PSC Input Mode 5: Stop signal and Insert Dead-Time .................................................... 123 12.14PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. ...................... 124 12.15PSC Input Mode 7: Halt PSC and Wait for Software Action .......................................... 124 12.16PSC Input Mode 8: Edge Retrigger PSC ......................................................................... 125 12.17PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC ............................................. 126 12.18PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate Output ...... 127 12.19PSC2 Outputs ................................................................................................................... 129 12.20Analog Synchronization ................................................................................................... 130 12.21Interrupt Handling ............................................................................................................ 130 12.22PSC Synchronization ........................................................................................................ 131 12.23PSC Clock Sources ........................................................................................................... 132 12.24Interrupts .......................................................................................................................... 132 12.25PSC Register Definition ................................................................................................... 133 12.26PSC2 Specific Register .................................................................................................... 142
13
Reduced Power Stage Controller - (PSCR) .......................................................147
13.1Features .............................................................................................................................. 147 13.2Overview ............................................................................................................................ 147 13.3PSCR Description ............................................................................................................. 148 13.4Signal Description .............................................................................................................. 149 13.5Functional Description ....................................................................................................... 151 13.6Update of Values ................................................................................................................ 154 13.7Enhanced resolution ........................................................................................................... 155 13.8PSCR Inputs ....................................................................................................................... 155 13.9PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait ...................... 161 13.10PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait .................... 162 13.11PSCR Input Mode 3: Stop signal, Execute Opposite while Fault active ......................... 163 13.12PSCR Input Mode 4: Deactivate outputs without changing timing. ................................ 164 13.13PSCR Input Mode 5: Stop signal and Insert Dead-Time ................................................. 164 13.14PSCR Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. ................... 165 13.15PSCR Input Mode 7: Halt PSCR and Wait for Software Action ..................................... 165 13.16PSCR Input Mode 8: Edge Retrigger PSC ....................................................................... 166 13.17PSCR Input Mode 9: Fixed Frequency Edge Retrigger PSC ........................................... 167 13.18PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate Output . 168 13.19Analog Synchronization ................................................................................................... 169
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13.20Interrupt Handling ............................................................................................................ 170 13.21PSC Clock Sources ........................................................................................................... 170 13.22Interrupts .......................................................................................................................... 171 13.23PSCR Register Definition ................................................................................................ 171
14
Serial Peripheral Interface - SPI: .....................................................................180
14.1Features .............................................................................................................................. 180 14.2Overview ............................................................................................................................ 180 14.3SS Pin Functionality ........................................................................................................... 184 14.4Data Modes ........................................................................................................................ 185 14.5SPI registers ........................................................................................................................ 186
15
Voltage Reference and Temperature Sensor .....................................................189
15.1Features .............................................................................................................................. 189 15.2On Chip voltage Reference and Temperature sensor overview ......................................... 189 15.3Register Description ........................................................................................................... 190 15.4Temperature Measurement ................................................................................................. 192
16
Analog Comparator ............................................................................................194
16.1Features .............................................................................................................................. 194 16.2Overview ............................................................................................................................ 194 16.3Shared pins between Analog Comparator and ADC .......................................................... 196 16.4Analog Comparator Register Description .......................................................................... 196
17
Analog to Digital Converter - ADC ....................................................................203
17.1Features .............................................................................................................................. 203 17.2Operation ............................................................................................................................ 205 17.3Starting a Conversion ......................................................................................................... 205 17.4Prescaling and Conversion Timing .................................................................................... 206 17.5Changing Channel or Reference Selection ......................................................................... 208 17.6ADC Noise Canceler .......................................................................................................... 209 17.7ADC Conversion Result ..................................................................................................... 214 17.8ADC Register Description ................................................................................................. 216 17.9Amplifier ............................................................................................................................ 221 17.10Amplifier Control Registers ............................................................................................. 224
18
Digital to Analog Converter - DAC ....................................................................226
18.1Features .............................................................................................................................. 226 18.2Operation ............................................................................................................................ 227
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7734P-AVR-08/10
18.3Starting a Conversion ......................................................................................................... 227 18.4DAC Register Description ................................................................................................. 228
19
debugWIRE On-chip Debug System ..................................................................231
19.1Features .............................................................................................................................. 231 19.2Overview ............................................................................................................................ 231 19.3Physical Interface ............................................................................................................... 231 19.4Software Break Points ........................................................................................................ 232 19.5Limitations of debugWIRE ................................................................................................ 232 19.6debugWIRE Related Register in I/O Memory ................................................................... 232
20
Boot Loader Support - Read-While-Write Self-Programming .........................232
20.1Boot Loader Features ......................................................................................................... 233 20.2Application and Boot Loader Flash Sections ..................................................................... 233 20.3Read-While-Write and No Read-While-Write Flash Sections .......................................... 233 20.4Boot Loader Lock Bits ....................................................................................................... 236 20.5Entering the Boot Loader Program .................................................................................... 237 20.6Addressing the Flash During Self-Programming ............................................................... 239 20.7Self-Programming the Flash ............................................................................................... 240
21
Memory Programming .......................................................................................247
21.1Program And Data Memory Lock Bits .............................................................................. 247 21.2Fuse Bits ............................................................................................................................. 249 21.3Signature Bytes .................................................................................................................. 252 21.4Calibration Byte ................................................................................................................. 252 21.5Parallel Programming Parameters, Pin Mapping, and Commands .................................... 252 21.6Serial Programming Pin Mapping ...................................................................................... 254 21.7Parallel Programming ......................................................................................................... 255 21.8Serial Downloading ............................................................................................................ 261
22
Electrical Characteristics(1) ..................................................................................................................... 265
22.1Absolute Maximum Ratings* ............................................................................................. 265 22.2DC Characteristics .............................................................................................................. 266 22.3Clock Drive Characteristics ............................................................................................... 270 22.4Maximum Speed vs. VCC
................................................................................................................................................. 271
22.5PLL Characteristics ............................................................................................................ 272 22.6SPI Timing Characteristics ................................................................................................. 273 22.7ADC Characteristics ........................................................................................................... 275 22.8DAC Characteristics ........................................................................................................... 277 v
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22.9Parallel Programming Characteristics ................................................................................ 277
23
AT90PWM81 Typical Characteristics ...............................................................280
23.1Active Supply Current ........................................................................................................ 281 23.2Idle Supply Current ............................................................................................................ 283 23.3Power-Down Supply Current ............................................................................................. 285 23.4Pin Pull-up .......................................................................................................................... 286 23.5Pin output high voltage ...................................................................................................... 289 23.6Pin output low voltage ........................................................................................................ 290 23.7Pin Thresholds .................................................................................................................... 291 23.8BOD Thresholds ................................................................................................................. 292 23.9Analog Reference ............................................................................................................... 293 23.10Internal Oscillator Speed .................................................................................................. 294 23.11Current Consumption in Reset ......................................................................................... 296
24 25 26 27
Register Summary ..............................................................................................298 Instruction Set Summary ...................................................................................302 Ordering Information .........................................................................................305 Package Information ..........................................................................................306
27.1SO20 ................................................................................................................................... 307 27.2QFN32 ................................................................................................................................ 308
28
Errata ..................................................................................................................309
28.1Errata AT90PWM81 revA ................................................................................................. 309 28.2Errata AT90PWM81 revB ................................................................................................. 309 28.3Errata AT90PWM81 revC ................................................................................................. 310 28.4Errata AT90PWM81 revD ................................................................................................. 312 28.5Errata AT90PWM81 revE .................................................................................................. 313
29
Datasheet Revision History for AT90PWM81 ...................................................315
29.1Rev. 7734A ......................................................................................................................... 315 29.2Rev. 7734B ......................................................................................................................... 315 29.3Rev. 7734C ......................................................................................................................... 315 29.4Rev. 7734D ......................................................................................................................... 315 29.5Rev. 7734E ......................................................................................................................... 315 29.6Rev. 7734F ......................................................................................................................... 316 29.7Rev. 7734G ......................................................................................................................... 316 29.8Rev. 7734H ......................................................................................................................... 316 vi
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29.9Rev. 7734I .......................................................................................................................... 316 29.10Rev. 7734J ........................................................................................................................ 317 29.11Rev. 7734K ....................................................................................................................... 317 29.12Rev. 7734L ....................................................................................................................... 317 29.13Rev. 7734M ...................................................................................................................... 317 29.14Rev. 7734N ....................................................................................................................... 317 29.15Rev. 7734O ....................................................................................................................... 317 29.16Rev. 7734P ....................................................................................................................... 317
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